From: Puyan Lotfi <puyan@puyan.org>
Date: Sun, 1 Sep 2019 00:45:28 +0000 (+0000)
Subject: [GlobalISel][NFC] Regression test cases for aarch64 legalizer (s128 sext+icmp).
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=5669c044fe6160889f938510e7013d0e5dd5036c;p=llvm

[GlobalISel][NFC] Regression test cases for aarch64 legalizer (s128 sext+icmp).

There were legalizer asserts in aarch64 globalisel (in debug mode) with s128
sext+icmp before r367060 and r366943 landed. These are just a couple reduced
mir and ir regression tests that came from a build where these were encountered.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370602 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.ll b/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.ll
new file mode 100644
index 00000000000..aff5245d905
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.ll
@@ -0,0 +1,9 @@
+; RUN: llc -O0 --global-isel=1 %s -o - -verify-machineinstrs
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+define i1 @foo(i64) {
+    %a = sext i64 %0 to i128
+    %b = icmp sle i128 %a, 0
+    ret i1 %b
+}
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.mir b/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.mir
new file mode 100644
index 00000000000..b1ccf02a572
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.mir
@@ -0,0 +1,23 @@
+# RUN: llc -o - --global-isel=1 -verify-machineinstrs -run-pass=legalizer -x mir %s
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-unknown-linux-gnu"
+  define i1 @foo(i64) {
+    %a = sext i64 %0 to i128
+    %b = icmp sle i128 %a, 0
+    ret i1 %b
+  }
+...
+---
+name:            foo
+body:             |
+  bb.1 (%ir-block.1):
+    liveins: $x0
+    %namedVReg4352:_(s64) = COPY $x0
+    %namedVReg1356:_(s128) = G_CONSTANT i128 0
+    %namedVReg1355:_(s128) = G_SEXT %namedVReg4352(s64)
+    %namedVReg1354:_(s1) = G_ICMP intpred(sle), %namedVReg1355(s128), %namedVReg1356
+    %namedVReg1353:_(s32) = G_SEXT %namedVReg1354(s1)
+    $w0 = COPY %namedVReg1353(s32)
+    RET_ReallyLR implicit $w0
+...