From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 27 Mar 2019 17:31:26 +0000 (+0000)
Subject: AMDGPU: Add testcase I meant to merge into r357093
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=5503f81d14fefaa85a00f5d70891b1d55ddd0066;p=llvm

AMDGPU: Add testcase I meant to merge into r357093

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357097 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/AMDGPU/spill-offset-calculation.ll b/test/CodeGen/AMDGPU/spill-offset-calculation.ll
index 14cbf5518e1..57722e202bc 100644
--- a/test/CodeGen/AMDGPU/spill-offset-calculation.ll
+++ b/test/CodeGen/AMDGPU/spill-offset-calculation.ll
@@ -48,6 +48,40 @@ entry:
   ret void
 }
 
+; CHECK-LABEL: test_sgpr_offset_kernel_scavenge_fail
+define amdgpu_kernel void @test_sgpr_offset_kernel_scavenge_fail() #1 {
+entry:
+  ; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
+  ; fit in the instruction, and has to live in the SGPR offset.
+  %alloca = alloca i8, i32 4092, align 4, addrspace(5)
+  %buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
+
+  %aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
+
+  ; 0x40000 / 64 = 4096 (for wave64)
+  %a = load volatile i32, i32 addrspace(5)* %aptr
+
+  %asm = call { i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "", "=s,=s,=s,=s,=s,=s,=s,=s"()
+  %asm0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 0
+  %asm1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 1
+  %asm2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 2
+  %asm3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 3
+  %asm4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 4
+  %asm5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 5
+  %asm6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 6
+  %asm7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32 } %asm, 7
+
+  call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0
+
+  ; CHECK: s_add_u32 s7, s7, 0x40000
+  ; CHECK: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s7 ; 4-byte Folded Reload
+  ; CHECK: s_sub_u32 s7, s7, 0x40000
+
+   ; Force %a to spill with no free SGPRs
+  call void asm sideeffect "", "s,s,s,s,s,s,s,s,v"(i32 %asm0, i32 %asm1, i32 %asm2, i32 %asm3, i32 %asm4, i32 %asm5, i32 %asm6, i32 %asm7, i32 %a)
+  ret void
+}
+
 ; CHECK-LABEL: test_sgpr_offset_subregs_kernel
 define amdgpu_kernel void @test_sgpr_offset_subregs_kernel() {
 entry:
@@ -207,3 +241,6 @@ entry:
 
   ret void
 }
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind "amdgpu-num-sgpr"="18" "amdgpu-num-vgpr"="8" }