From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 16 Sep 2019 00:37:10 +0000 (+0000)
Subject: AMDGPU/GlobalISel: Legalize s1 source G_[SU]ITOFP
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=54dea4c5eed0b17e93e5bda681b6221536638d4e;p=llvm

AMDGPU/GlobalISel: Legalize s1 source G_[SU]ITOFP

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371952 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index a4301b5405a..abfb4525935 100644
--- a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -415,8 +415,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
                {S32, S8}, {S128, S32}, {S128, S64}, {S32, LLT::scalar(24)}})
     .scalarize(0);
 
+  // TODO: Legal for s1->s64, requires split for VALU.
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
-    .legalFor({{S32, S32}, {S64, S32}, {S16, S32}})
+    .legalFor({{S32, S32}, {S64, S32}, {S16, S32}, {S32, S1}, {S16, S1}})
     .lowerFor({{S32, S64}})
     .customFor({{S64, S64}})
     .scalarize(0);
diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
index e48292127d5..aedfc8d1c4d 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
@@ -29,3 +29,39 @@ body: |
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_SITOFP %0
 ...
+
+---
+name: sitofp_s_s1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: sitofp_s_s1
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
+    ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[ICMP]](s1)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s32) = G_CONSTANT i32 0
+    %2:_(s1) = G_ICMP intpred(eq), %0, %1
+    %3:_(s32) = G_SITOFP %2
+...
+
+---
+name: sitofp_v_s1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: sitofp_v_s1
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
+    ; CHECK: [[SITOFP:%[0-9]+]]:vgpr(s32) = G_SITOFP [[ICMP]](s1)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = G_CONSTANT i32 0
+    %2:_(s1) = G_ICMP intpred(eq), %0, %1
+    %3:_(s32) = G_SITOFP %2
+...
diff --git a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
index 07f47c559a7..bb0054bb25e 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
@@ -29,3 +29,39 @@ body: |
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = G_UITOFP %0
 ...
+
+---
+name: uitofp_s_s1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: uitofp_s_s1
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
+    ; CHECK: [[UITOFP:%[0-9]+]]:vgpr(s32) = G_UITOFP [[ICMP]](s1)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s32) = G_CONSTANT i32 0
+    %2:_(s1) = G_ICMP intpred(eq), %0, %1
+    %3:_(s32) = G_UITOFP %2
+...
+
+---
+name: uitofp_v_s1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: uitofp_v_s1
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
+    ; CHECK: [[UITOFP:%[0-9]+]]:vgpr(s32) = G_UITOFP [[ICMP]](s1)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = G_CONSTANT i32 0
+    %2:_(s1) = G_ICMP intpred(eq), %0, %1
+    %3:_(s32) = G_UITOFP %2
+...