From: Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Date: Sun, 26 May 2019 19:50:31 +0000 (+0000)
Subject: [MCA][Scheduler] Improved critical memory dependency computation.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=54b0b36a76fcfb0cacce15148a2a38f476cb1eef;p=llvm

[MCA][Scheduler] Improved critical memory dependency computation.

This fixes a problem where back-pressure increases caused by register
dependencies were not correctly notified if execution was also delayed by memory
dependencies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361740 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/MCA/HardwareUnits/Scheduler.cpp b/lib/MCA/HardwareUnits/Scheduler.cpp
index b2928ed1b12..6b3448fbe82 100644
--- a/lib/MCA/HardwareUnits/Scheduler.cpp
+++ b/lib/MCA/HardwareUnits/Scheduler.cpp
@@ -105,7 +105,13 @@ void Scheduler::issueInstruction(
   // other dependent instructions. Dependent instructions may be issued during
   // this same cycle if operands have ReadAdvance entries.  Promote those
   // instructions to the ReadySet and notify the caller that those are ready.
-  if (HasDependentUsers && promoteToPendingSet(PendingInstructions))
+  // If IR is a memory operation, then always call method `promoteToReadySet()`
+  // to notify any dependent memory operations that IR started execution.
+  bool ShouldPromoteInstructions = Inst.isMemOp();
+  if (HasDependentUsers)
+    ShouldPromoteInstructions |= promoteToPendingSet(PendingInstructions);
+
+  if (ShouldPromoteInstructions)
     promoteToReadySet(ReadyInstructions);
 }
 
@@ -287,15 +293,19 @@ uint64_t Scheduler::analyzeResourcePressure(SmallVectorImpl<InstRef> &Insts) {
 void Scheduler::analyzeDataDependencies(SmallVectorImpl<InstRef> &RegDeps,
                                         SmallVectorImpl<InstRef> &MemDeps) {
   const auto EndIt = PendingSet.end() - NumDispatchedToThePendingSet;
-  for (InstRef &IR : make_range(PendingSet.begin(), EndIt)) {
-    Instruction &IS = *IR.getInstruction();
+  for (const InstRef &IR : make_range(PendingSet.begin(), EndIt)) {
+    const Instruction &IS = *IR.getInstruction();
     if (Resources->checkAvailability(IS.getDesc()))
       continue;
 
-    if (IS.isReady() || (IS.isMemOp() && LSU.isReady(IR) != IR))
-      MemDeps.emplace_back(IR);
-    else
+    const CriticalDependency &CMD = IS.getCriticalMemDep();
+    if (IS.isMemOp() && IS.getCurrentMemDep() != &IS && !CMD.Cycles)
+      continue;
+
+    if (IS.isPending())
       RegDeps.emplace_back(IR);
+    if (CMD.Cycles)
+      MemDeps.emplace_back(IR);
   }
 }
 
diff --git a/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s b/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s
index 6cd613a52fc..bedfef1d95f 100644
--- a/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s
+++ b/test/tools/llvm-mca/X86/BtVer2/bottleneck-hints-3.s
@@ -24,7 +24,7 @@ vmovaps %xmm0, 48(%rdi)
 # CHECK-NEXT: Throughput Bottlenecks:
 # CHECK-NEXT:   Resource Pressure       [ 0.00% ]
 # CHECK-NEXT:   Data Dependencies:      [ 99.89% ]
-# CHECK-NEXT:   - Register Dependencies [ 0.00% ]
+# CHECK-NEXT:   - Register Dependencies [ 83.24% ]
 # CHECK-NEXT:   - Memory Dependencies   [ 99.89% ]
 
 # CHECK:      Instruction Info: