From: Daniel Sanders Date: Thu, 3 Jan 2019 00:14:33 +0000 (+0000) Subject: [tblgen][disasm] Emit record names again when decoder conflicts occur. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=5367c025826523075c62b90413442d9fc6b18b4e;p=llvm [tblgen][disasm] Emit record names again when decoder conflicts occur. And add a test for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350277 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/TableGen/FixedLenDecoderEmitter/conflict.td b/test/TableGen/FixedLenDecoderEmitter/conflict.td new file mode 100644 index 00000000000..a9a95bc05a3 --- /dev/null +++ b/test/TableGen/FixedLenDecoderEmitter/conflict.td @@ -0,0 +1,35 @@ +// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t +// RUN: FileCheck %s < %t + +include "llvm/Target/Target.td" + +def MyTargetISA : InstrInfo; +def MyTarget : Target { let InstructionSet = MyTargetISA; } + +def R0 : Register<"r0"> { let Namespace = "MyTarget"; } +def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>; + +class I Pat> + : Instruction { + let Namespace = "MyTarget"; + let OutOperandList = OOps; + let InOperandList = IOps; + let Pattern = Pat; + bits<32> Inst; + bits<32> SoftFail; +} + +def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> { + let Size = 4; + let Inst{31-0} = 0; +} +def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> { + let Size = 4; + let Inst{31-0} = 0; +} + +// CHECK: Decoding Conflict: +// CHECK: 00000000000000000000000000000000 +// CHECK: ................................ +// CHECK: A 00000000000000000000000000000000 +// CHECK: B 00000000000000000000000000000000 diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp index 1206f7751a9..5e621fc0efd 100644 --- a/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -1717,7 +1717,7 @@ void FilterChooser::emitTableEntries(DecoderTableInfo &TableInfo) const { dumpStack(errs(), "\t\t"); for (unsigned i = 0; i < Opcodes.size(); ++i) { - errs() << '\t' << Opcodes[i] << " "; + errs() << '\t' << AllInstructions[Opcodes[i]] << " "; dumpBits(errs(), getBitsField(*AllInstructions[Opcodes[i]].EncodingDef, "Inst")); errs() << '\n';