From: JF Bastien Date: Thu, 25 Jul 2019 16:11:57 +0000 (+0000) Subject: Allow prefetching from non-zero address spaces X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=53274294b9f1040d92112ea9d2c42c7754f4766a;p=clang Allow prefetching from non-zero address spaces Summary: This is useful for targets which have prefetch instructions for non-default address spaces. Subscribers: nemanjai, javed.absar, hiraditya, kbarton, jkorous, dexonsmith, cfe-commits, llvm-commits, RKSimon, hfinkel, t.p.northover, craig.topper, anemet Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65254 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@367032 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/CGBuiltin.cpp b/lib/CodeGen/CGBuiltin.cpp index 82c089e722..aaa196f806 100644 --- a/lib/CodeGen/CGBuiltin.cpp +++ b/lib/CodeGen/CGBuiltin.cpp @@ -2133,7 +2133,7 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, Locality = (E->getNumArgs() > 2) ? EmitScalarExpr(E->getArg(2)) : llvm::ConstantInt::get(Int32Ty, 3); Value *Data = llvm::ConstantInt::get(Int32Ty, 1); - Function *F = CGM.getIntrinsic(Intrinsic::prefetch); + Function *F = CGM.getIntrinsic(Intrinsic::prefetch, Address->getType()); return RValue::get(Builder.CreateCall(F, {Address, RW, Locality, Data})); } case Builtin::BI__builtin_readcyclecounter: { @@ -6021,7 +6021,7 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID, // Locality is not supported on ARM target Value *Locality = llvm::ConstantInt::get(Int32Ty, 3); - Function *F = CGM.getIntrinsic(Intrinsic::prefetch); + Function *F = CGM.getIntrinsic(Intrinsic::prefetch, Address->getType()); return Builder.CreateCall(F, {Address, RW, Locality, IsData}); } @@ -6960,7 +6960,7 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID, // FIXME: We need AArch64 specific LLVM intrinsic if we want to specify // PLDL3STRM or PLDL2STRM. - Function *F = CGM.getIntrinsic(Intrinsic::prefetch); + Function *F = CGM.getIntrinsic(Intrinsic::prefetch, Address->getType()); return Builder.CreateCall(F, {Address, RW, Locality, IsData}); } @@ -10037,7 +10037,7 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID, Value *RW = ConstantInt::get(Int32Ty, (C->getZExtValue() >> 2) & 0x1); Value *Locality = ConstantInt::get(Int32Ty, C->getZExtValue() & 0x3); Value *Data = ConstantInt::get(Int32Ty, 1); - Function *F = CGM.getIntrinsic(Intrinsic::prefetch); + Function *F = CGM.getIntrinsic(Intrinsic::prefetch, Address->getType()); return Builder.CreateCall(F, {Address, RW, Locality, Data}); } case X86::BI_mm_clflush: { diff --git a/lib/Sema/SemaExpr.cpp b/lib/Sema/SemaExpr.cpp index 401bb3c000..8f5a892b9a 100644 --- a/lib/Sema/SemaExpr.cpp +++ b/lib/Sema/SemaExpr.cpp @@ -5375,8 +5375,8 @@ static FunctionDecl *rewriteBuiltinFunctionDecl(Sema *Sema, ASTContext &Context, QualType DeclType = FDecl->getType(); const FunctionProtoType *FT = dyn_cast(DeclType); - if (!Context.BuiltinInfo.hasPtrArgsOrResult(FDecl->getBuiltinID()) || - !FT || FT->isVariadic() || ArgExprs.size() != FT->getNumParams()) + if (!Context.BuiltinInfo.hasPtrArgsOrResult(FDecl->getBuiltinID()) || !FT || + ArgExprs.size() < FT->getNumParams()) return nullptr; bool NeedsNewDecl = false; @@ -5415,6 +5415,7 @@ static FunctionDecl *rewriteBuiltinFunctionDecl(Sema *Sema, ASTContext &Context, return nullptr; FunctionProtoType::ExtProtoInfo EPI; + EPI.Variadic = FT->isVariadic(); QualType OverloadTy = Context.getFunctionType(FT->getReturnType(), OverloadParams, EPI); DeclContext *Parent = FDecl->getParent(); diff --git a/test/CodeGen/arm_acle.c b/test/CodeGen/arm_acle.c index beca937350..2f086ee70b 100644 --- a/test/CodeGen/arm_acle.c +++ b/test/CodeGen/arm_acle.c @@ -88,28 +88,28 @@ void test_swp(uint32_t x, volatile void *p) { /* 8.6 Memory prefetch intrinsics */ /* 8.6.1 Data prefetch */ // ARM-LABEL: test_pld -// ARM: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 1) +// ARM: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 1) void test_pld() { __pld(0); } // ARM-LABEL: test_pldx -// AArch32: call void @llvm.prefetch(i8* null, i32 1, i32 3, i32 1) -// AArch64: call void @llvm.prefetch(i8* null, i32 1, i32 1, i32 1) +// AArch32: call void @llvm.prefetch.p0i8(i8* null, i32 1, i32 3, i32 1) +// AArch64: call void @llvm.prefetch.p0i8(i8* null, i32 1, i32 1, i32 1) void test_pldx() { __pldx(1, 2, 0, 0); } /* 8.6.2 Instruction prefetch */ // ARM-LABEL: test_pli -// ARM: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 0) +// ARM: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0) void test_pli() { __pli(0); } // ARM-LABEL: test_plix -// AArch32: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 0) -// AArch64: call void @llvm.prefetch(i8* null, i32 0, i32 1, i32 0) +// AArch32: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0) +// AArch64: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 1, i32 0) void test_plix() { __plix(2, 0, 0); } diff --git a/test/CodeGen/builtins-arm.c b/test/CodeGen/builtins-arm.c index 020f2b4dc5..4941411bfb 100644 --- a/test/CodeGen/builtins-arm.c +++ b/test/CodeGen/builtins-arm.c @@ -92,14 +92,13 @@ unsigned rbit(unsigned a) { void prefetch(int i) { __builtin_arm_prefetch(&i, 0, 1); -// CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 0, i32 3, i32 1) + // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* %{{.*}}, i32 0, i32 3, i32 1) __builtin_arm_prefetch(&i, 1, 1); -// CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 1, i32 3, i32 1) - + // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* %{{.*}}, i32 1, i32 3, i32 1) __builtin_arm_prefetch(&i, 1, 0); -// CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 1, i32 3, i32 0) + // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* %{{.*}}, i32 1, i32 3, i32 0) } void ldc(const void *i) { diff --git a/test/CodeGen/builtins-arm64.c b/test/CodeGen/builtins-arm64.c index 5ec63fba82..7095396e6b 100644 --- a/test/CodeGen/builtins-arm64.c +++ b/test/CodeGen/builtins-arm64.c @@ -46,16 +46,16 @@ void barriers() { void prefetch() { __builtin_arm_prefetch(0, 1, 2, 0, 1); // pstl3keep -// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 1, i32 1, i32 1) + // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* null, i32 1, i32 1, i32 1) __builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1keep -// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 0, i32 1) + // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* null, i32 0, i32 0, i32 1) __builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1strm -// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 0, i32 1) + // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* null, i32 0, i32 0, i32 1) __builtin_arm_prefetch(0, 0, 0, 0, 0); // plil1keep -// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 3, i32 0) + // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0) } int32_t jcvt(double v) { diff --git a/test/CodeGen/ppc-xmmintrin.c b/test/CodeGen/ppc-xmmintrin.c index fd81937da6..094f18efcb 100644 --- a/test/CodeGen/ppc-xmmintrin.c +++ b/test/CodeGen/ppc-xmmintrin.c @@ -1435,7 +1435,7 @@ test_prefetch() { // CHECK: store i8* {{[0-9a-zA-Z_%.]+}}, i8** {{[0-9a-zA-Z_%.]+}}, align 8 // CHECK-NEXT: store i32 {{[0-9a-zA-Z_%.]+}}, i32* {{[0-9a-zA-Z_%.]+}}, align 4 // CHECK-NEXT: [[REG715:[0-9a-zA-Z_%.]+]] = load i8*, i8** {{[0-9a-zA-Z_%.]+}}, align 8 -// CHECK-NEXT: call void @llvm.prefetch(i8* [[REG715]], i32 0, i32 3, i32 1) +// CHECK-NEXT: call void @llvm.prefetch.p0i8(i8* [[REG715]], i32 0, i32 3, i32 1) // CHECK-NEXT: ret void void __attribute__((noinline)) diff --git a/test/CodeGen/pr9614.c b/test/CodeGen/pr9614.c index 63cb5af186..08089848ee 100644 --- a/test/CodeGen/pr9614.c +++ b/test/CodeGen/pr9614.c @@ -34,7 +34,7 @@ void f(void) { // CHECK: call void @foo() // CHECK: call i32 @abs(i32 0) // CHECK: call i8* @strrchr( -// CHECK: call void @llvm.prefetch( +// CHECK: call void @llvm.prefetch.p0i8( // CHECK: call i8* @memchr( // CHECK: ret void @@ -42,4 +42,4 @@ void f(void) { // CHECK: declare i32 @abs(i32 // CHECK: declare i8* @strrchr(i8*, i32) // CHECK: declare i8* @memchr( -// CHECK: declare void @llvm.prefetch( +// CHECK: declare void @llvm.prefetch.p0i8( diff --git a/test/CodeGen/prefetch-addr-spaces.c b/test/CodeGen/prefetch-addr-spaces.c new file mode 100644 index 0000000000..87810621f1 --- /dev/null +++ b/test/CodeGen/prefetch-addr-spaces.c @@ -0,0 +1,6 @@ +// RUN: %clang_cc1 -triple x86_64-pc-linux -emit-llvm %s -o - | FileCheck %s + +void f(int __attribute__((address_space(1))) * a, ...) { + __builtin_prefetch(a, 0, 1); + // CHECK: call void @llvm.prefetch.p1i8(i8 addrspace(1)* {{%.+}}, i32 0, i32 1, i32 1) +} diff --git a/test/CodeGen/prefetchw-builtins.c b/test/CodeGen/prefetchw-builtins.c index 53416de46f..b3a8062acf 100644 --- a/test/CodeGen/prefetchw-builtins.c +++ b/test/CodeGen/prefetchw-builtins.c @@ -5,12 +5,12 @@ void test_m_prefetch(void *p) { return _m_prefetch(p); -// CHECK-LABEL: define void @test_m_prefetch -// CHECK: call void @llvm.prefetch({{.*}}, i32 0, i32 3, i32 1) + // CHECK-LABEL: define void @test_m_prefetch + // CHECK: call void @llvm.prefetch.p0i8({{.*}}, i32 0, i32 3, i32 1) } void test_m_prefetch_w(void *p) { return _m_prefetchw(p); -// CHECK-LABEL: define void @test_m_prefetch_w -// CHECK: call void @llvm.prefetch({{.*}}, i32 1, i32 3, i32 1) + // CHECK-LABEL: define void @test_m_prefetch_w + // CHECK: call void @llvm.prefetch.p0i8({{.*}}, i32 1, i32 3, i32 1) } diff --git a/test/CodeGen/sse-builtins.c b/test/CodeGen/sse-builtins.c index 4179341fad..b68a714b43 100644 --- a/test/CodeGen/sse-builtins.c +++ b/test/CodeGen/sse-builtins.c @@ -503,7 +503,7 @@ __m128 test_mm_or_ps(__m128 A, __m128 B) { void test_mm_prefetch(char const* p) { // CHECK-LABEL: test_mm_prefetch - // CHECK: call void @llvm.prefetch(i8* {{.*}}, i32 0, i32 0, i32 1) + // CHECK: call void @llvm.prefetch.p0i8(i8* {{.*}}, i32 0, i32 0, i32 1) _mm_prefetch(p, 0); }