From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 27 Mar 2019 18:14:02 +0000 (+0000)
Subject: RegPressure: Fix crash on blocks with only dbg_value
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=53202c3a192df50a73067bade05cf58e6fa1e379;p=llvm

RegPressure: Fix crash on blocks with only dbg_value

If there were only dbg_values in the block, recede would hit the
beginning of the block and try to use thet dbg_value as a real
instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357105 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/RegisterPressure.cpp b/lib/CodeGen/RegisterPressure.cpp
index dafd95fa7d5..7d9b3aa9b2d 100644
--- a/lib/CodeGen/RegisterPressure.cpp
+++ b/lib/CodeGen/RegisterPressure.cpp
@@ -845,7 +845,7 @@ void RegPressureTracker::recedeSkipDebugValues() {
   CurrPos = skipDebugInstructionsBackward(std::prev(CurrPos), MBB->begin());
 
   SlotIndex SlotIdx;
-  if (RequireIntervals)
+  if (RequireIntervals && !CurrPos->isDebugInstr())
     SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
 
   // Open the top of the region using slot indexes.
@@ -855,6 +855,12 @@ void RegPressureTracker::recedeSkipDebugValues() {
 
 void RegPressureTracker::recede(SmallVectorImpl<RegisterMaskPair> *LiveUses) {
   recedeSkipDebugValues();
+  if (CurrPos->isDebugValue()) {
+    // It's possible to only have debug_value instructions and hit the start of
+    // the block.
+    assert(CurrPos == MBB->begin());
+    return;
+  }
 
   const MachineInstr &MI = *CurrPos;
   RegisterOperands RegOpers;
diff --git a/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir b/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
new file mode 100644
index 00000000000..9850500874c
--- /dev/null
+++ b/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
@@ -0,0 +1,135 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s
+--- |
+
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #0
+
+  define amdgpu_kernel void @could_not_use_debug_inst_to_query_mi2mimap() #1 {
+    ret void
+  }
+
+  declare hidden float @foo(float, float, float) local_unnamed_addr #1
+
+  attributes #0 = { nounwind readnone speculatable }
+  attributes #1 = {nounwind }
+
+...
+---
+name:            could_not_use_debug_inst_to_query_mi2mimap
+tracksRegLiveness: true
+frameInfo:
+  hasCalls:        true
+body:             |
+  ; CHECK-LABEL: name: could_not_use_debug_inst_to_query_mi2mimap
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+  ; CHECK:   [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 1082130432, [[DEF1]], implicit $exec
+  ; CHECK:   [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   DBG_VALUE
+  ; CHECK:   DBG_VALUE
+  ; CHECK:   DBG_VALUE
+  ; CHECK: bb.2:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   S_BRANCH %bb.3
+  ; CHECK: bb.3:
+  ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  ; CHECK:   [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]
+  ; CHECK:   [[V_MUL_F32_e32_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $exec
+  ; CHECK:   [[V_MUL_F32_e32_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $exec
+  ; CHECK:   [[V_MUL_F32_e32_3:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $exec
+  ; CHECK:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
+  ; CHECK:   [[DEF13:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; CHECK:   [[V_ADD_F32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $exec
+  ; CHECK:   [[V_MUL_F32_e32_4:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $exec
+  ; CHECK:   dead %23:vgpr_32 = V_MUL_F32_e32 [[V_MUL_F32_e32_4]], [[DEF13]], implicit $exec
+  ; CHECK:   dead [[V_MOV_B32_e32_1]]:vgpr_32 = V_MAC_F32_e32 [[V_ADD_F32_e32_]], [[COPY]], [[V_MOV_B32_e32_1]], implicit $exec
+  ; CHECK:   [[DEF14:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
+  ; CHECK:   $sgpr4 = IMPLICIT_DEF
+  ; CHECK:   $vgpr0 = COPY [[DEF11]]
+  ; CHECK:   $vgpr0 = COPY [[V_MOV_B32_e32_]]
+  ; CHECK:   $vgpr1 = COPY [[DEF7]]
+  ; CHECK:   $vgpr0 = COPY [[V_MUL_F32_e32_1]]
+  ; CHECK:   $vgpr1 = COPY [[V_MUL_F32_e32_2]]
+  ; CHECK:   $vgpr2 = COPY [[V_MUL_F32_e32_3]]
+  ; CHECK:   dead $sgpr30_sgpr31 = SI_CALL [[DEF14]], @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit-def $vgpr0
+  ; CHECK:   [[V_ADD_F32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_F32_e32 [[V_MUL_F32_e32_]], [[DEF8]], implicit $exec
+  ; CHECK:   [[V_MAC_F32_e32_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e32 [[DEF12]], [[DEF9]], [[V_MAC_F32_e32_]], implicit $exec
+  ; CHECK:   dead %26:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF4]], 0, [[DEF1]], 0, 0, implicit $exec
+  ; CHECK:   dead %27:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF5]], 0, [[DEF2]], 0, 0, implicit $exec
+  ; CHECK:   dead %28:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF6]], 0, [[DEF3]], 0, 0, implicit $exec
+  ; CHECK:   GLOBAL_STORE_DWORD [[DEF]], [[DEF10]], 0, 0, 0, implicit $exec
+  ; CHECK:   S_ENDPGM 0
+  bb.0:
+    successors: %bb.1
+
+    %0:vreg_64 = IMPLICIT_DEF
+    %1:vgpr_32 = IMPLICIT_DEF
+    %2:vgpr_32 = IMPLICIT_DEF
+    %3:vgpr_32 = IMPLICIT_DEF
+    %4:vgpr_32 = IMPLICIT_DEF
+    %5:vgpr_32 = IMPLICIT_DEF
+    %6:vgpr_32 = IMPLICIT_DEF
+    %7:vgpr_32 = IMPLICIT_DEF
+    %8:vgpr_32 = IMPLICIT_DEF
+    %9:vgpr_32 = V_MUL_F32_e32 1082130432, %1, implicit $exec
+    %10:vgpr_32 = IMPLICIT_DEF
+    %11:vgpr_32 = IMPLICIT_DEF
+
+  bb.1:
+    successors: %bb.2
+
+    DBG_VALUE
+    DBG_VALUE
+    DBG_VALUE
+
+  bb.2:
+    successors: %bb.3
+
+    S_BRANCH %bb.3
+
+  bb.3:
+    %12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %13:vgpr_32 = COPY %12
+    %14:vgpr_32 = IMPLICIT_DEF
+    %15:vgpr_32 = IMPLICIT_DEF
+    %16:vgpr_32 = V_MUL_F32_e32 %7, %7, implicit $exec
+    %17:vgpr_32 = V_MUL_F32_e32 %7, %7, implicit $exec
+    %18:vgpr_32 = V_MUL_F32_e32 %12, %12, implicit $exec
+    %19:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
+    %20:vgpr_32 = IMPLICIT_DEF
+    %21:vgpr_32 = V_ADD_F32_e32 %12, %12, implicit $exec
+    %22:vgpr_32 = V_MUL_F32_e32 %7, %7, implicit $exec
+    %23:vgpr_32 = V_MUL_F32_e32 %22, %20, implicit $exec
+    %19:vgpr_32 = V_MAC_F32_e32 %21, %13, %19, implicit $exec
+    %24:sreg_64 = IMPLICIT_DEF
+    $vgpr0 = COPY %14
+    $vgpr0 = COPY %12
+    $vgpr1 = COPY %7
+    $vgpr0 = COPY %16
+    $vgpr1 = COPY %17
+    $vgpr2 = COPY %18
+    $sgpr4 = IMPLICIT_DEF
+    dead $sgpr30_sgpr31 = SI_CALL %24, @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit killed $vgpr0, implicit killed $vgpr1, implicit killed $vgpr2, implicit-def $vgpr0
+    %25:vgpr_32 = V_ADD_F32_e32 %9, %8, implicit $exec
+    %25:vgpr_32 = V_MAC_F32_e32 %15, %10, %25, implicit $exec
+    %26:vgpr_32 = V_MAD_F32 0, %25, 0, %4, 0, %1, 0, 0, implicit $exec
+    %27:vgpr_32 = V_MAD_F32 0, %25, 0, %5, 0, %2, 0, 0, implicit $exec
+    %28:vgpr_32 = V_MAD_F32 0, %25, 0, %6, 0, %3, 0, 0, implicit $exec
+    GLOBAL_STORE_DWORD %0, %11, 0, 0, 0, implicit $exec
+    S_ENDPGM 0
+
+...