From: Tom Stellard Date: Fri, 13 Jul 2018 21:05:14 +0000 (+0000) Subject: AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.exp X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=504eed44cd3c122eaf0b3d85ad2282c7d0e09467;p=llvm AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.exp Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45882 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337046 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 73b7241e447..7db6edc5575 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -115,6 +115,10 @@ AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO, } } +static int64_t getConstant(const MachineInstr *MI) { + return MI->getOperand(1).getCImm()->getSExtValue(); +} + bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const { MachineBasicBlock *BB = I.getParent(); MachineFunction *MF = BB->getParent(); @@ -208,6 +212,69 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I, return false; } +static MachineInstr * +buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt, + unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, + unsigned VM, bool Compr, unsigned Enabled, bool Done) { + const DebugLoc &DL = Insert->getDebugLoc(); + MachineBasicBlock &BB = *Insert->getParent(); + unsigned Opcode = Done ? AMDGPU::EXP_DONE : AMDGPU::EXP; + return BuildMI(BB, Insert, DL, TII.get(Opcode)) + .addImm(Tgt) + .addReg(Reg0) + .addReg(Reg1) + .addReg(Reg2) + .addReg(Reg3) + .addImm(VM) + .addImm(Compr) + .addImm(Enabled); +} + +bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS( + MachineInstr &I, + CodeGenCoverage &CoverageInfo) const { + MachineBasicBlock *BB = I.getParent(); + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + + unsigned IntrinsicID = I.getOperand(0).getIntrinsicID(); + switch (IntrinsicID) { + case Intrinsic::amdgcn_exp: { + int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg())); + int64_t Enabled = getConstant(MRI.getVRegDef(I.getOperand(2).getReg())); + int64_t Done = getConstant(MRI.getVRegDef(I.getOperand(7).getReg())); + int64_t VM = getConstant(MRI.getVRegDef(I.getOperand(8).getReg())); + + MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(), + I.getOperand(4).getReg(), + I.getOperand(5).getReg(), + I.getOperand(6).getReg(), + VM, false, Enabled, Done); + + I.eraseFromParent(); + return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI); + } + case Intrinsic::amdgcn_exp_compr: { + const DebugLoc &DL = I.getDebugLoc(); + int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg())); + int64_t Enabled = getConstant(MRI.getVRegDef(I.getOperand(2).getReg())); + unsigned Reg0 = I.getOperand(3).getReg(); + unsigned Reg1 = I.getOperand(4).getReg(); + unsigned Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + int64_t Done = getConstant(MRI.getVRegDef(I.getOperand(5).getReg())); + int64_t VM = getConstant(MRI.getVRegDef(I.getOperand(6).getReg())); + + BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef); + MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM, + true, Enabled, Done); + + I.eraseFromParent(); + return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI); + } + } + return false; +} + bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const { MachineBasicBlock *BB = I.getParent(); MachineFunction *MF = BB->getParent(); @@ -573,6 +640,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, return selectG_IMPLICIT_DEF(I); case TargetOpcode::G_INTRINSIC: return selectG_INTRINSIC(I, CoverageInfo); + case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: + return selectG_INTRINSIC_W_SIDE_EFFECTS(I, CoverageInfo); case TargetOpcode::G_LOAD: return selectG_LOAD(I); case TargetOpcode::G_STORE: diff --git a/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index 0ffbc2e4edf..68b40b20aca 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -68,6 +68,8 @@ private: bool selectG_GEP(MachineInstr &I) const; bool selectG_IMPLICIT_DEF(MachineInstr &I) const; bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; + bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I, + CodeGenCoverage &CoverageInfo) const; bool hasVgprParts(ArrayRef AddrInfo) const; void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, SmallVectorImpl &AddrInfo) const; diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir new file mode 100644 index 00000000000..071625f98c0 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir @@ -0,0 +1,33 @@ +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- +name: exp0 +legalized: true +regBankSelected: true + +# CHECK: name: exp0 +body: | + bb.0: + liveins: $vgpr0 + %0:vgpr(s32) = COPY $vgpr0 + %1:sgpr(s32) = G_CONSTANT i32 1 + %2:sgpr(s32) = G_CONSTANT i32 15 + %3:sgpr(s1) = G_CONSTANT i1 0 + %4:sgpr(s1) = G_CONSTANT i1 1 + + ; CHECK: EXP 1, %0, %0, %0, %0, 0, 0, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %1:sgpr(s32), %2:sgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %3:sgpr(s1), %3:sgpr(s1) + + ; CHECK: EXP_DONE 1, %0, %0, %0, %0, 0, 0, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %1:sgpr(s32), %2:sgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %4:sgpr(s1), %3:sgpr(s1) + + %5:vgpr(<2 x s16>) = G_BITCAST %0(s32) + + ; CHECK: [[UNDEF0:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK: EXP 1, %0, %0, [[UNDEF0]], [[UNDEF0]], 0, 1, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), %1:sgpr(s32), %2:sgpr(s32), %5:vgpr(<2 x s16>), %5:vgpr(<2 x s16>), %3:sgpr(s1), %3:sgpr(s1) + + ; CHECK: [[UNDEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK: EXP_DONE 1, %0, %0, [[UNDEF1]], [[UNDEF1]], 0, 1, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), %1:sgpr(s32), %2:sgpr(s32), %5:vgpr(<2 x s16>), %5:vgpr(<2 x s16>), %4:sgpr(s1), %3:sgpr(s1) +