From: Simon Tatham <simon.tatham@arm.com>
Date: Fri, 28 Jun 2019 09:28:39 +0000 (+0000)
Subject: [ARM] Fix integer UB in MVE load/store immediate handling.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=4f77b3ddf353ea63dad95d74e7d453b34efcc4c3;p=llvm

[ARM] Fix integer UB in MVE load/store immediate handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364635 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 9fb2fa65fdd..673691ebd93 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4182,7 +4182,7 @@ static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
   else if (!(Val & 0x80))
     imm *= -1;
   if (imm != INT32_MIN)
-    imm <<= shift;
+    imm *= (1U << shift);
   Inst.addOperand(MCOperand::createImm(imm));
 
   return MCDisassembler::Success;
@@ -4448,7 +4448,7 @@ static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
       imm *= -1;
   }
   if (imm != INT32_MIN)
-    imm <<= shift;
+    imm *= (1U << shift);
   Inst.addOperand(MCOperand::createImm(imm));
 
   return S;
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index c506f267731..dca6fe37d49 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -1621,12 +1621,15 @@ getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
   // If the immediate is B bits long, we need B+1 bits in order
   // to represent the (inverse of the) sign bit.
   Value <<= (Bits + 1);
-  int32_t tmp = (int32_t)MO2.getImm() >> Shift;
-  if (tmp < 0)
+  int32_t tmp = (int32_t)MO2.getImm();
+  if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
+    tmp = 0;
+  } else if (tmp < 0) {
     tmp = abs(tmp);
-  else
+  } else {
     Value |= (1U << Bits); // Set the ADD bit
-  Value |= tmp & ((1U << Bits) - 1);
+  }
+  Value |= (tmp >> Shift) & ((1U << Bits) - 1);
   return Value;
 }