From: Artem Belevich Date: Wed, 9 May 2018 23:10:09 +0000 (+0000) Subject: [CUDA] Added -f[no-]cuda-short-ptr option X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=4f482660272cb79d5bec53291b043b0b9b19c29e;p=clang [CUDA] Added -f[no-]cuda-short-ptr option The option enables use of 32-bit pointers for accessing const/local/shared memory. The feature is disabled by default. Differential Revision: https://reviews.llvm.org/D46148 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@331938 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/clang/Basic/TargetOptions.h b/include/clang/Basic/TargetOptions.h index cbe0953e74..31a6742879 100644 --- a/include/clang/Basic/TargetOptions.h +++ b/include/clang/Basic/TargetOptions.h @@ -63,6 +63,10 @@ public: /// If given, enables support for __int128_t and __uint128_t types. bool ForceEnableInt128 = false; + + /// \brief If enabled, use 32-bit pointers for accessing const/local/shared + /// address space. + bool NVPTXUseShortPointers = false; }; } // end namespace clang diff --git a/include/clang/Driver/Options.td b/include/clang/Driver/Options.td index 52f2e34621..95ae9625d3 100644 --- a/include/clang/Driver/Options.td +++ b/include/clang/Driver/Options.td @@ -581,6 +581,9 @@ def fno_cuda_approx_transcendentals : Flag<["-"], "fno-cuda-approx-transcendenta def fcuda_rdc : Flag<["-"], "fcuda-rdc">, Flags<[CC1Option]>, HelpText<"Generate relocatable device code, also known as separate compilation mode.">; def fno_cuda_rdc : Flag<["-"], "fno-cuda-rdc">; +def fcuda_short_ptr : Flag<["-"], "fcuda-short-ptr">, Flags<[CC1Option]>, + HelpText<"Use 32-bit pointers for accessing const/local/shared address spaces.">; +def fno_cuda_short_ptr : Flag<["-"], "fno-cuda-short-ptr">; def dA : Flag<["-"], "dA">, Group; def dD : Flag<["-"], "dD">, Group, Flags<[CC1Option]>, HelpText<"Print macro definitions in -E mode in addition to normal output">; diff --git a/lib/Basic/Targets/NVPTX.cpp b/lib/Basic/Targets/NVPTX.cpp index 04293b3ce1..fd4ee16060 100644 --- a/lib/Basic/Targets/NVPTX.cpp +++ b/lib/Basic/Targets/NVPTX.cpp @@ -68,6 +68,9 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple, if (TargetPointerWidth == 32) resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"); + else if (Opts.NVPTXUseShortPointers) + resetDataLayout( + "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"); else resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64"); diff --git a/lib/Driver/ToolChains/Clang.cpp b/lib/Driver/ToolChains/Clang.cpp index 4165afcfa9..cc26b5e04e 100644 --- a/lib/Driver/ToolChains/Clang.cpp +++ b/lib/Driver/ToolChains/Clang.cpp @@ -4714,6 +4714,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, if (Args.hasFlag(options::OPT_fcuda_rdc, options::OPT_fno_cuda_rdc, false)) CmdArgs.push_back("-fcuda-rdc"); + if (Args.hasFlag(options::OPT_fcuda_short_ptr, + options::OPT_fno_cuda_short_ptr, false)) + CmdArgs.push_back("-fcuda-short-ptr"); } // OpenMP offloading device jobs take the argument -fopenmp-host-ir-file-path diff --git a/lib/Driver/ToolChains/Cuda.cpp b/lib/Driver/ToolChains/Cuda.cpp index 3978cb2742..5916ad033c 100644 --- a/lib/Driver/ToolChains/Cuda.cpp +++ b/lib/Driver/ToolChains/Cuda.cpp @@ -635,8 +635,10 @@ void CudaToolChain::addClangTargetOptions( // CUDA-9.0 uses new instructions that are only available in PTX6.0+ PtxFeature = "+ptx60"; } - CC1Args.push_back("-target-feature"); - CC1Args.push_back(PtxFeature); + CC1Args.append({"-target-feature", PtxFeature}); + if (DriverArgs.hasFlag(options::OPT_fcuda_short_ptr, + options::OPT_fno_cuda_short_ptr, false)) + CC1Args.append({"-mllvm", "--nvptx-short-ptr"}); if (DeviceOffloadingKind == Action::OFK_OpenMP) { SmallVector LibraryPaths; diff --git a/lib/Frontend/CompilerInvocation.cpp b/lib/Frontend/CompilerInvocation.cpp index 71c946442d..05e5196e32 100644 --- a/lib/Frontend/CompilerInvocation.cpp +++ b/lib/Frontend/CompilerInvocation.cpp @@ -2922,6 +2922,8 @@ static void ParseTargetArgs(TargetOptions &Opts, ArgList &Args, Opts.Triple = llvm::sys::getDefaultTargetTriple(); Opts.OpenCLExtensionsAsWritten = Args.getAllArgValues(OPT_cl_ext_EQ); Opts.ForceEnableInt128 = Args.hasArg(OPT_fforce_enable_int128); + Opts.NVPTXUseShortPointers = Args.hasFlag( + options::OPT_fcuda_short_ptr, options::OPT_fno_cuda_short_ptr, false); } bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,