From: Craig Topper Date: Sat, 18 Feb 2017 22:53:43 +0000 (+0000) Subject: [X86][XOP] Reduce the size of a multiclass by moving more stuff to parameters instead... X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=4deede4ddbdcf57bc8d6f69bffbee8150838f239;p=llvm [X86][XOP] Reduce the size of a multiclass by moving more stuff to parameters instead of doing 128-bit and 256-bit simultaneously. This requires some instructions to be renamed to move the Y earlier in the instruction name. The new names are more consistent with other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295579 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86InstrFragmentsSIMD.td b/lib/Target/X86/X86InstrFragmentsSIMD.td index 196ba39e8ac..5a95c61633f 100644 --- a/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -239,6 +239,7 @@ def X86vpermil2 : SDNode<"X86ISD::VPERMIL2", SDTCisSameAs<0,2>, SDTCisSameSizeAs<0,3>, SDTCisSameNumEltsAs<0, 3>, + SDTCisFP<0>, SDTCisInt<3>, SDTCisVT<4, i8>]>>; def X86vpperm : SDNode<"X86ISD::VPPERM", SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 01cacb44b82..4efcfada427 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1787,9 +1787,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VPCOMUQri, X86::VPCOMUQmi, 0 }, { X86::VPCOMUWri, X86::VPCOMUWmi, 0 }, { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 }, - { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 }, + { X86::VPERMIL2PDYrr, X86::VPERMIL2PDYmr, 0 }, { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 }, - { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 }, + { X86::VPERMIL2PSYrr, X86::VPERMIL2PSYmr, 0 }, { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 }, { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 }, { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 }, @@ -2480,9 +2480,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 }, { X86::VPCMOVYrrr, X86::VPCMOVYrrm, 0 }, { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 }, - { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 }, + { X86::VPERMIL2PDYrr, X86::VPERMIL2PDYrm, 0 }, { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 }, - { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 }, + { X86::VPERMIL2PSYrr, X86::VPERMIL2PSYrm, 0 }, { X86::VPPERMrrr, X86::VPPERMrrm, 0 }, // AVX-512 instructions with 3 source operands. diff --git a/lib/Target/X86/X86InstrXOP.td b/lib/Target/X86/X86InstrXOP.td index bd8a700595c..53224431c0e 100644 --- a/lib/Target/X86/X86InstrXOP.td +++ b/lib/Target/X86/X86InstrXOP.td @@ -292,7 +292,6 @@ let ExeDomain = SSEPackedInt in { // Instruction where either second or third source can be memory multiclass xop4op_int opc, string OpcodeStr, RegisterClass RC, X86MemOperand x86memop, ValueType VT> { - // 128-bit Instruction def rrr : IXOPi8Reg, VEX_L; } -multiclass xop5op opc, string OpcodeStr, SDNode OpNode, - ValueType vt128, ValueType vt256, - ValueType id128, ValueType id256, - PatFrag ld_128, PatFrag ld_256> { - def rr : IXOP5 Opc, string OpcodeStr, RegisterClass RC, + X86MemOperand intmemop, X86MemOperand fpmemop, + ValueType VT, PatFrag FPLdFrag, + PatFrag IntLdFrag> { + def rr : IXOP5; - def rm : IXOP5; + def rm : IXOP5, - VEX_W; - def mr : IXOP5, VEX_W; + def mr : IXOP5; + [(set RC:$dst, + (VT (X86vpermil2 RC:$src1, (FPLdFrag addr:$src2), + RC:$src3, (i8 imm:$src4))))]>; // For disassembler let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in - def rr_REV : IXOP5, VEX_W; - - def rrY : IXOP5, VEX_L; - def rmY : IXOP5, VEX_W, VEX_L; - def mrY : IXOP5, VEX_L; - // For disassembler - let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in - def rrY_REV : IXOP5, VEX_W, VEX_L; } -let ExeDomain = SSEPackedDouble in - defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", X86vpermil2, v2f64, v4f64, - v2i64, v4i64, loadv2f64, loadv4f64>; +let ExeDomain = SSEPackedDouble in { + defm VPERMIL2PD : xop_vpermil2<0x49, "vpermil2pd", VR128, i128mem, f128mem, + v2f64, loadv2f64, loadv2i64>; + defm VPERMIL2PDY : xop_vpermil2<0x49, "vpermil2pd", VR256, i256mem, f256mem, + v4f64, loadv4f64, loadv4i64>, VEX_L; +} -let ExeDomain = SSEPackedSingle in - defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", X86vpermil2, v4f32, v8f32, - v4i32, v8i32, loadv4f32, loadv8f32>; +let ExeDomain = SSEPackedSingle in { + defm VPERMIL2PS : xop_vpermil2<0x48, "vpermil2ps", VR128, i128mem, f128mem, + v4f32, loadv4f32, loadv2i64>; + defm VPERMIL2PSY : xop_vpermil2<0x48, "vpermil2ps", VR256, i256mem, f256mem, + v8f32, loadv8f32, loadv4i64>, VEX_L; +} diff --git a/lib/Target/X86/X86MCInstLower.cpp b/lib/Target/X86/X86MCInstLower.cpp index 65949531126..55b090b6764 100644 --- a/lib/Target/X86/X86MCInstLower.cpp +++ b/lib/Target/X86/X86MCInstLower.cpp @@ -1607,8 +1607,8 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { case X86::VPERMIL2PDrm: case X86::VPERMIL2PSrm: - case X86::VPERMIL2PDrmY: - case X86::VPERMIL2PSrmY: { + case X86::VPERMIL2PDYrm: + case X86::VPERMIL2PSYrm: { if (!OutStreamer->isVerboseAsm()) break; assert(MI->getNumOperands() >= 8 && @@ -1621,8 +1621,8 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned ElSize; switch (MI->getOpcode()) { default: llvm_unreachable("Invalid opcode"); - case X86::VPERMIL2PSrm: case X86::VPERMIL2PSrmY: ElSize = 32; break; - case X86::VPERMIL2PDrm: case X86::VPERMIL2PDrmY: ElSize = 64; break; + case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break; + case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break; } const MachineOperand &MaskOp = MI->getOperand(6);