From: Daniel Sanders <daniel_l_sanders@apple.com>
Date: Sat, 22 Apr 2017 15:53:21 +0000 (+0000)
Subject: [globalisel][tablegen] Add support for RegisterOperand.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=4a4290955c1bc948d9935c2d6fee52504448b891;p=llvm

[globalisel][tablegen] Add support for RegisterOperand.

Summary:
It functions just like RegisterClass except that the class is obtained
from a field.

Depends on D31761.

Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar

Reviewed By: ab

Subscribers: dberris, llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D32229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301080 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/TableGen/GlobalISelEmitter.td b/test/TableGen/GlobalISelEmitter.td
index c3ce530d431..8d59036100a 100644
--- a/test/TableGen/GlobalISelEmitter.td
+++ b/test/TableGen/GlobalISelEmitter.td
@@ -9,6 +9,7 @@ def MyTarget : Target { let InstructionSet = MyTargetISA; }
 
 def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+def GPR32Op : RegisterOperand<GPR32>;
 
 class I<dag OOps, dag IOps, list<dag> Pat>
   : Instruction {
@@ -91,7 +92,7 @@ def HasB : Predicate<"Subtarget->hasB()">;
 // CHECK-NEXT:        }
 
 def : GINodeEquiv<G_SELECT, select>;
-def INSN2 : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2, complex:$src3), []>;
+def INSN2 : I<(outs GPR32:$dst), (ins GPR32Op:$src1, complex:$src2, complex:$src3), []>;
 def : Pat<(select GPR32:$src1, complex:$src2, complex:$src3),
           (INSN2 GPR32:$src1, complex:$src3, complex:$src2)>;
 
diff --git a/utils/TableGen/GlobalISelEmitter.cpp b/utils/TableGen/GlobalISelEmitter.cpp
index b637114a2e0..e2b120e1347 100644
--- a/utils/TableGen/GlobalISelEmitter.cpp
+++ b/utils/TableGen/GlobalISelEmitter.cpp
@@ -1384,6 +1384,12 @@ Error GlobalISelEmitter::importChildMatcher(InstructionMatcher &InsnMatcher,
       return Error::success();
     }
 
+    if (ChildRec->isSubClassOf("RegisterOperand")) {
+      OM.addPredicate<RegisterBankOperandMatcher>(
+          Target.getRegisterClass(ChildRec->getValueAsDef("RegClass")));
+      return Error::success();
+    }
+
     // Check for ComplexPattern's.
     if (ChildRec->isSubClassOf("ComplexPattern")) {
       const auto &ComplexPattern = ComplexPatternEquivs.find(ChildRec);
@@ -1447,7 +1453,8 @@ Error GlobalISelEmitter::importExplicitUseRenderer(
       return Error::success();
     }
 
-    if (ChildRec->isSubClassOf("RegisterClass")) {
+    if (ChildRec->isSubClassOf("RegisterClass") ||
+        ChildRec->isSubClassOf("RegisterOperand")) {
       DstMIBuilder.addRenderer<CopyRenderer>(InsnMatcher, DstChild->getName());
       return Error::success();
     }
@@ -1614,6 +1621,8 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
 
     const auto &DstIOperand = DstI.Operands[OpIdx];
     Record *DstIOpRec = DstIOperand.Rec;
+    if (DstIOpRec->isSubClassOf("RegisterOperand"))
+      DstIOpRec = DstIOpRec->getValueAsDef("RegClass");
     if (!DstIOpRec->isSubClassOf("RegisterClass"))
       return failedImport("Dst MI def isn't a register class");