From: Sam Parker <sam.parker@arm.com>
Date: Mon, 23 Sep 2019 08:35:31 +0000 (+0000)
Subject: [ARM][LowOverheadLoops] Use tBcc when reverting
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=4a1b357783020a4bf1c4ae6d617ac2123e6805e9;p=llvm

[ARM][LowOverheadLoops] Use tBcc when reverting

Check the branch target ranges and use a tBcc instead of t2Bcc when
we can.

Differential Revision: https://reviews.llvm.org/D67796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372557 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMLowOverheadLoops.cpp b/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 09f540fcfde..c1aa21520a4 100644
--- a/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -354,8 +354,7 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
 
 // WhileLoopStart holds the exit block, so produce a cmp lr, 0 and then a
 // beq that branches to the exit branch.
-// FIXME: Need to check that we're not trashing the CPSR when generating the
-// cmp. We could also try to generate a cbz if the value in LR is also in
+// TODO: We could also try to generate a cbz if the value in LR is also in
 // another low register.
 void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
   LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp: " << *MI);
@@ -366,9 +365,12 @@ void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
   MIB.addImm(0);
   MIB.addImm(ARMCC::AL);
   MIB.addReg(ARM::NoRegister);
+  
+  MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
+  unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
+    ARM::tBcc : ARM::t2Bcc;
 
-  // TODO: Try to use tBcc instead
-  MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
+  MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
   MIB.add(MI->getOperand(1));   // branch target
   MIB.addImm(ARMCC::EQ);        // condition code
   MIB.addReg(ARM::CPSR);
@@ -391,8 +393,6 @@ void ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI) const {
 }
 
 // Generate a subs, or sub and cmp, and a branch instead of an LE.
-// FIXME: Need to check that we're not trashing the CPSR when generating
-// the cmp.
 void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
   LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp, br: " << *MI);
 
@@ -405,9 +405,12 @@ void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
   MIB.addImm(ARMCC::AL);
   MIB.addReg(ARM::NoRegister);
 
-  // TODO Try to use tBcc instead.
+  MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
+  unsigned BrOpc = BBUtils->isBBInRange(MI, DestBB, 254) ?
+    ARM::tBcc : ARM::t2Bcc;
+
   // Create bne
-  MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
+  MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
   MIB.add(MI->getOperand(1));   // branch target
   MIB.addImm(ARMCC::NE);        // condition code
   MIB.addReg(ARM::CPSR);
diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll b/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
index 17b7b63c0c4..c36845b5f26 100644
--- a/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
+++ b/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
@@ -16,7 +16,7 @@
 ; CHECK-END: .LBB0_2:
 ; CHECK-END:   sub.w lr, lr, #1
 ; CHECK-END:   cmp.w lr, #0
-; CHECK-END:   bne.w .LBB0_3
+; CHECK-END:   bne .LBB0_3
 ; CHECK-END:   b .LBB0_4
 ; CHECK-END: .LBB0_3:
 ; CHECK-END:   b .LBB0_2
diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir b/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
index 82c533b8bdf..259a4c9a7f7 100644
--- a/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
+++ b/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
@@ -4,7 +4,7 @@
 # CHECK-NOT: DLS
 # CHECK: bb.1.for.body:
 # CHECK:   t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
-# CHECK:   t2Bcc %bb.3, 1, $cpsr
+# CHECK:   tBcc %bb.3, 1, $cpsr
 # CHECK:   tB %bb.2, 14, $noreg
 # CHECK: bb.2.for.cond.cleanup:
 # CHECK: bb.3.for.header:
diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir b/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
index 751bcbf3ea5..0d48a4a858c 100644
--- a/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
+++ b/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
@@ -3,7 +3,7 @@
 # CHECK: bb.5.for.inc16:
 # CHECK:   $lr = t2SUBri killed renamable $lr, 1, 14
 # CHECK:   t2CMPri $lr, 0, 14
-# CHECK:   t2Bcc %bb.6, 1
+# CHECK:   tBcc %bb.6, 1
 # CHECK:   tB %bb.2
 # CHECK: bb.6.for.cond4.preheader:
 
diff --git a/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir b/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
index da171f5387a..a7c1876d9c5 100644
--- a/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
+++ b/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
@@ -5,11 +5,11 @@
 # CHECK:   tBcc %bb.2, 3
 # CHECK: bb.1.not.preheader:
 # CHECK:   t2CMPri renamable $lr, 0, 14
-# CHECK:   t2Bcc %bb.4, 0
+# CHECK:   tBcc %bb.4, 0
 # CHECK:   tB %bb.2
 # CHECK: bb.3.while.body:
 # CHECK:   t2CMPri $lr, 0, 14
-# CHECK:   t2Bcc %bb.3, 1
+# CHECK:   tBcc %bb.3, 1
 # CHECK:   tB %bb.4
 # CHECK: bb.4.while.end: