From: Alex Bradbury <asb@lowrisc.org>
Date: Thu, 7 Dec 2017 12:45:05 +0000 (+0000)
Subject: [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/loadReadFr... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=499f980e9e5e2b84f9d7947d0b8ddfb7ed4ab9f4;p=llvm

[RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/loadReadFromStackSlot

Simply checking for register class equality will break once additional
register classes are added (as is done for the RVC instruction set extension).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320036 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/RISCV/RISCVInstrInfo.cpp b/lib/Target/RISCV/RISCVInstrInfo.cpp
index 5b4f4fcbb88..186fe363edd 100644
--- a/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -52,7 +52,7 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  if (RC == &RISCV::GPRRegClass)
+  if (RISCV::GPRRegClass.hasSubClassEq(RC))
     BuildMI(MBB, I, DL, get(RISCV::SW))
         .addReg(SrcReg, getKillRegState(IsKill))
         .addFrameIndex(FI)
@@ -70,7 +70,7 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  if (RC == &RISCV::GPRRegClass)
+  if (RISCV::GPRRegClass.hasSubClassEq(RC))
     BuildMI(MBB, I, DL, get(RISCV::LW), DstReg).addFrameIndex(FI).addImm(0);
   else
     llvm_unreachable("Can't load this register from stack slot");