From: Simon Pilgrim Date: Sun, 2 Jul 2017 12:56:10 +0000 (+0000) Subject: [X86][SSE] Add test showing missed opportunity to combine to pshuflw X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=496650c94d165c4ac51e1a9491a96f04f59dabc0;p=llvm [X86][SSE] Add test showing missed opportunity to combine to pshuflw We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306976 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll b/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll index 546b7312603..242872329a3 100644 --- a/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll +++ b/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll @@ -445,6 +445,24 @@ define <16 x i8> @combine_pshufb_not_as_pshufw(<16 x i8> %a0) { ret <16 x i8> %res1 } +; TODO - we could fold the load if we lowered to pshuflw instead. +define <16 x i8> @combine_vpshufb_as_pshuflw_not_pslld(<16 x i8> *%a0) { +; SSE-LABEL: combine_vpshufb_as_pshuflw_not_pslld: +; SSE: # BB#0: +; SSE-NEXT: movdqa (%rdi), %xmm0 +; SSE-NEXT: pslld $16, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: combine_vpshufb_as_pshuflw_not_pslld: +; AVX: # BB#0: +; AVX-NEXT: vmovdqa (%rdi), %xmm0 +; AVX-NEXT: vpslld $16, %xmm0, %xmm0 +; AVX-NEXT: retq + %res0 = load <16 x i8>, <16 x i8> *%a0, align 16 + %res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> ) + ret <16 x i8> %res1 +} + define <16 x i8> @combine_pshufb_as_unary_unpcklbw(<16 x i8> %a0) { ; SSE-LABEL: combine_pshufb_as_unary_unpcklbw: ; SSE: # BB#0: