From: Simon Pilgrim Date: Wed, 26 Apr 2017 13:03:00 +0000 (+0000) Subject: [X86] Added pointer math zext test case (PR22970) X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=4886bbbe7131761f2ab46f5e413ca24c13d130d9;p=llvm [X86] Added pointer math zext test case (PR22970) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301401 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/X86/pr22970.ll b/test/CodeGen/X86/pr22970.ll new file mode 100644 index 00000000000..38c063355f6 --- /dev/null +++ b/test/CodeGen/X86/pr22970.ll @@ -0,0 +1,47 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 + +define i32 @PR22970_i32(i32* nocapture readonly, i32) { +; X86-LABEL: PR22970_i32: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl $4095, %ecx # imm = 0xFFF +; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl 32(%eax,%ecx,4), %eax +; X86-NEXT: retl +; +; X64-LABEL: PR22970_i32: +; X64: # BB#0: +; X64-NEXT: # kill: %ESI %ESI %RSI +; X64-NEXT: andl $4095, %esi # imm = 0xFFF +; X64-NEXT: movl 32(%rdi,%rsi,4), %eax +; X64-NEXT: retq + %3 = and i32 %1, 4095 + %4 = add nuw nsw i32 %3, 8 + %5 = zext i32 %4 to i64 + %6 = getelementptr inbounds i32, i32* %0, i64 %5 + %7 = load i32, i32* %6, align 4 + ret i32 %7 +} + +define i32 @PR22970_i64(i32* nocapture readonly, i64) { +; X86-LABEL: PR22970_i64: +; X86: # BB#0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl $4095, %ecx # imm = 0xFFF +; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl 32(%eax,%ecx,4), %eax +; X86-NEXT: retl +; +; X64-LABEL: PR22970_i64: +; X64: # BB#0: +; X64-NEXT: andl $4095, %esi # imm = 0xFFF +; X64-NEXT: movl 32(%rdi,%rsi,4), %eax +; X64-NEXT: retq + %3 = and i64 %1, 4095 + %4 = add nuw nsw i64 %3, 8 + %5 = getelementptr inbounds i32, i32* %0, i64 %4 + %6 = load i32, i32* %5, align 4 + ret i32 %6 +}