From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Tue, 21 May 2019 23:23:05 +0000 (+0000)
Subject: AMDGPU: Fix not marking new gfx10 SGPRs as CSRs
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=4865fdf345935a0e63a19a6d2d59cd147c033614;p=llvm

AMDGPU: Fix not marking new gfx10 SGPRs as CSRs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361330 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPUCallingConv.td b/lib/Target/AMDGPU/AMDGPUCallingConv.td
index 8389058e3f7..8fdb97500ca 100644
--- a/lib/Target/AMDGPU/AMDGPUCallingConv.td
+++ b/lib/Target/AMDGPU/AMDGPUCallingConv.td
@@ -110,12 +110,12 @@ def CSR_AMDGPU_VGPRs_32_255 : CalleeSavedRegs<
   (sequence "VGPR%u", 32, 255)
 >;
 
-def CSR_AMDGPU_SGPRs_32_103 : CalleeSavedRegs<
-  (sequence "SGPR%u", 32, 103)
+def CSR_AMDGPU_SGPRs_32_105 : CalleeSavedRegs<
+  (sequence "SGPR%u", 32, 105)
 >;
 
 def CSR_AMDGPU_HighRegs : CalleeSavedRegs<
-  (add CSR_AMDGPU_VGPRs_32_255, CSR_AMDGPU_SGPRs_32_103)
+  (add CSR_AMDGPU_VGPRs_32_255, CSR_AMDGPU_SGPRs_32_105)
 >;
 
 // Calling convention for leaf functions
diff --git a/test/CodeGen/AMDGPU/csr-gfx10.ll b/test/CodeGen/AMDGPU/csr-gfx10.ll
new file mode 100644
index 00000000000..17855568ed9
--- /dev/null
+++ b/test/CodeGen/AMDGPU/csr-gfx10.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
+
+; Make sure new higher SGPRs are callee saved
+; GFX10-LABEL: {{^}}callee_new_sgprs:
+; GFX10: v_writelane_b32 v0, s104, 0
+; GFX10: v_writelane_b32 v0, s105, 1
+; GFX10: ; clobber s104
+; GFX10: ; clobber s105
+; GFX10: v_readlane_b32 s105, v0, 1
+; GFX10: v_readlane_b32 s104, v0, 0
+define void @callee_new_sgprs() {
+  call void asm sideeffect "; clobber s104", "~{s104}"()
+  call void asm sideeffect "; clobber s105", "~{s105}"()
+  ret void
+}