From: Cullen Rhodes <cullen.rhodes@arm.com>
Date: Fri, 17 May 2019 09:19:41 +0000 (+0000)
Subject: [AArch64][SVE2] Asm: add integer multiply-add long instructions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=4735a38358d51bd0567df613061febf305d4dbd4;p=llvm

[AArch64][SVE2] Asm: add integer multiply-add long instructions

Summary:
Patch adds support for indexed and unpredicated vectors forms of the
following instructions:

    * SMLALB, SMLALT, UMLALB, UMLALT, SMLSLB, SMLSLT, UMLSLB, UMLSLT

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: rovka

Differential Revision: https://reviews.llvm.org/D61951


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361003 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 5685a75dd23..5535d784289 100644
--- a/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1077,6 +1077,26 @@ let Predicates = [HasSVE2] in {
   defm SQDMULLB_ZZZI : sve2_int_mul_long_by_indexed_elem<0b100, "sqdmullb">;
   defm SQDMULLT_ZZZI : sve2_int_mul_long_by_indexed_elem<0b101, "sqdmullt">;
 
+  // SVE2 integer multiply-add long (indexed)
+  defm SMLALB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1000, "smlalb">;
+  defm SMLALT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1001, "smlalt">;
+  defm UMLALB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1010, "umlalb">;
+  defm UMLALT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1011, "umlalt">;
+  defm SMLSLB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1100, "smlslb">;
+  defm SMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1101, "smlslt">;
+  defm UMLSLB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1110, "umlslb">;
+  defm UMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1111, "umlslt">;
+
+  // SVE2 integer multiply-add long (vectors, unpredicated)
+  defm SMLALB_ZZZ : sve2_int_mla_long<0b10000, "smlalb">;
+  defm SMLALT_ZZZ : sve2_int_mla_long<0b10001, "smlalt">;
+  defm UMLALB_ZZZ : sve2_int_mla_long<0b10010, "umlalb">;
+  defm UMLALT_ZZZ : sve2_int_mla_long<0b10011, "umlalt">;
+  defm SMLSLB_ZZZ : sve2_int_mla_long<0b10100, "smlslb">;
+  defm SMLSLT_ZZZ : sve2_int_mla_long<0b10101, "smlslt">;
+  defm UMLSLB_ZZZ : sve2_int_mla_long<0b10110, "umlslb">;
+  defm UMLSLT_ZZZ : sve2_int_mla_long<0b10111, "umlslt">;
+
   // SVE2 integer multiply long
   defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">;
   defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">;
diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td
index 8b07ccdba4b..c0d3ff03890 100644
--- a/lib/Target/AArch64/SVEInstrFormats.td
+++ b/lib/Target/AArch64/SVEInstrFormats.td
@@ -1722,6 +1722,12 @@ multiclass sve2_int_mla<bit S, string asm> {
   def _D : sve2_int_mla<0b11, { 0b1110, S }, asm, ZPR64, ZPR64>;
 }
 
+multiclass sve2_int_mla_long<bits<5> opc, string asm> {
+  def _H : sve2_int_mla<0b01, opc, asm, ZPR16, ZPR8>;
+  def _S : sve2_int_mla<0b10, opc, asm, ZPR32, ZPR16>;
+  def _D : sve2_int_mla<0b11, opc, asm, ZPR64, ZPR32>;
+}
+
 //===----------------------------------------------------------------------===//
 // SVE2 Integer Multiply-Add - Indexed Group
 //===----------------------------------------------------------------------===//
@@ -1767,6 +1773,29 @@ multiclass sve2_int_mla_by_indexed_elem<bits<2> opc, bit S, string asm> {
   }
 }
 
+//===----------------------------------------------------------------------===//
+// SVE2 Integer Multiply-Add Long - Indexed Group
+//===----------------------------------------------------------------------===//
+
+multiclass sve2_int_mla_long_by_indexed_elem<bits<4> opc, string asm> {
+  def _S : sve2_int_mla_by_indexed_elem<0b10, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
+                                        asm, ZPR32, ZPR16, ZPR3b16, VectorIndexH> {
+    bits<3> Zm;
+    bits<3> iop;
+    let Inst{20-19} = iop{2-1};
+    let Inst{18-16} = Zm;
+    let Inst{11} = iop{0};
+  }
+  def _D : sve2_int_mla_by_indexed_elem<0b11, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
+                                        asm, ZPR64, ZPR32, ZPR4b32, VectorIndexS> {
+    bits<4> Zm;
+    bits<2> iop;
+    let Inst{20} = iop{1};
+    let Inst{19-16} = Zm;
+    let Inst{11} = iop{0};
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // SVE Integer Dot Product Group
 //===----------------------------------------------------------------------===//
diff --git a/test/MC/AArch64/SVE2/smlalb-diagnostics.s b/test/MC/AArch64/SVE2/smlalb-diagnostics.s
new file mode 100644
index 00000000000..3dd03fc67f8
--- /dev/null
+++ b/test/MC/AArch64/SVE2/smlalb-diagnostics.s
@@ -0,0 +1,116 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+smlalb z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlalb z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.d, z1.s, z16.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlalb z0.d, z1.s, z16.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+smlalb z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlalb z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlalb z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.d, z1.s, z15.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: smlalb z0.d, z1.s, z15.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.d, z1.s, z15.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: smlalb z0.d, z1.s, z15.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+smlalb z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.b, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.b, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.h, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.h, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.d, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.d, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.d, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.d, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalb z0.d, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalb z0.d, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+smlalb  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: smlalb  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.d, p0/z, z7.d
+smlalb  z0.d, z1.s, z15.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: smlalb  z0.d, z1.s, z15.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/test/MC/AArch64/SVE2/smlalb.s b/test/MC/AArch64/SVE2/smlalb.s
new file mode 100644
index 00000000000..069e98447a4
--- /dev/null
+++ b/test/MC/AArch64/SVE2/smlalb.s
@@ -0,0 +1,67 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+smlalb z0.h, z1.b, z31.b
+// CHECK-INST: smlalb	z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x40,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 40 5f 44 <unknown>
+
+smlalb z0.s, z1.h, z31.h
+// CHECK-INST: smlalb	z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x40,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 40 9f 44 <unknown>
+
+smlalb z0.d, z1.s, z31.s
+// CHECK-INST: smlalb	z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x40,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 40 df 44 <unknown>
+
+smlalb z0.s, z1.h, z7.h[7]
+// CHECK-INST: smlalb	z0.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0x88,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 88 bf 44 <unknown>
+
+smlalb z0.d, z1.s, z15.s[1]
+// CHECK-INST: smlalb	z0.d, z1.s, z15.s[1]
+// CHECK-ENCODING: [0x20,0x88,0xef,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 88 ef 44 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+smlalb z21.d, z1.s, z31.s
+// CHECK-INST: smlalb	z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0x40,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 40 df 44 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+smlalb   z21.d, z10.s, z5.s[1]
+// CHECK-INST: smlalb   z21.d, z10.s, z5.s[1]
+// CHECK-ENCODING: [0x55,0x89,0xe5,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 55 89 e5 44 <unknown>
diff --git a/test/MC/AArch64/SVE2/smlalt-diagnostics.s b/test/MC/AArch64/SVE2/smlalt-diagnostics.s
new file mode 100644
index 00000000000..e0753ba7480
--- /dev/null
+++ b/test/MC/AArch64/SVE2/smlalt-diagnostics.s
@@ -0,0 +1,116 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+smlalt z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlalt z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.d, z1.s, z16.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlalt z0.d, z1.s, z16.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+smlalt z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlalt z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlalt z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.d, z1.s, z15.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: smlalt z0.d, z1.s, z15.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.d, z1.s, z15.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: smlalt z0.d, z1.s, z15.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+smlalt z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.b, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.b, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.h, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.h, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.d, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.d, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.d, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.d, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlalt z0.d, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlalt z0.d, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+smlalt  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: smlalt  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.d, p0/z, z7.d
+smlalt  z0.d, z1.s, z15.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: smlalt  z0.d, z1.s, z15.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/test/MC/AArch64/SVE2/smlalt.s b/test/MC/AArch64/SVE2/smlalt.s
new file mode 100644
index 00000000000..43192dcb1b9
--- /dev/null
+++ b/test/MC/AArch64/SVE2/smlalt.s
@@ -0,0 +1,67 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+smlalt z0.h, z1.b, z31.b
+// CHECK-INST: smlalt	z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x44,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 44 5f 44 <unknown>
+
+smlalt z0.s, z1.h, z31.h
+// CHECK-INST: smlalt	z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x44,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 44 9f 44 <unknown>
+
+smlalt z0.d, z1.s, z31.s
+// CHECK-INST: smlalt	z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x44,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 44 df 44 <unknown>
+
+smlalt z0.s, z1.h, z7.h[7]
+// CHECK-INST: smlalt	z0.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0x8c,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 8c bf 44 <unknown>
+
+smlalt z0.d, z1.s, z15.s[1]
+// CHECK-INST: smlalt	z0.d, z1.s, z15.s[1]
+// CHECK-ENCODING: [0x20,0x8c,0xef,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 8c ef 44 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+smlalt z21.d, z1.s, z31.s
+// CHECK-INST: smlalt	z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0x44,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 44 df 44 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+smlalt   z21.d, z10.s, z5.s[1]
+// CHECK-INST: smlalt   z21.d, z10.s, z5.s[1]
+// CHECK-ENCODING: [0x55,0x8d,0xe5,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 55 8d e5 44 <unknown>
diff --git a/test/MC/AArch64/SVE2/smlslb-diagnostics.s b/test/MC/AArch64/SVE2/smlslb-diagnostics.s
new file mode 100644
index 00000000000..bb8d5c80880
--- /dev/null
+++ b/test/MC/AArch64/SVE2/smlslb-diagnostics.s
@@ -0,0 +1,116 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+smlslb z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlslb z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.d, z1.s, z16.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlslb z0.d, z1.s, z16.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+smlslb z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlslb z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlslb z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.d, z1.s, z15.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: smlslb z0.d, z1.s, z15.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.d, z1.s, z15.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: smlslb z0.d, z1.s, z15.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+smlslb z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.b, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.b, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.h, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.h, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.d, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.d, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.d, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.d, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslb z0.d, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslb z0.d, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+smlslb  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: smlslb  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.d, p0/z, z7.d
+smlslb  z0.d, z1.s, z15.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: smlslb  z0.d, z1.s, z15.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/test/MC/AArch64/SVE2/smlslb.s b/test/MC/AArch64/SVE2/smlslb.s
new file mode 100644
index 00000000000..34aa1ebdbbf
--- /dev/null
+++ b/test/MC/AArch64/SVE2/smlslb.s
@@ -0,0 +1,67 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+smlslb z0.h, z1.b, z31.b
+// CHECK-INST: smlslb	z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x50,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 50 5f 44 <unknown>
+
+smlslb z0.s, z1.h, z31.h
+// CHECK-INST: smlslb	z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x50,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 50 9f 44 <unknown>
+
+smlslb z0.d, z1.s, z31.s
+// CHECK-INST: smlslb	z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x50,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 50 df 44 <unknown>
+
+smlslb z0.s, z1.h, z7.h[7]
+// CHECK-INST: smlslb	z0.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0xa8,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 a8 bf 44 <unknown>
+
+smlslb z0.d, z1.s, z15.s[1]
+// CHECK-INST: smlslb	z0.d, z1.s, z15.s[1]
+// CHECK-ENCODING: [0x20,0xa8,0xef,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 a8 ef 44 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+smlslb z21.d, z1.s, z31.s
+// CHECK-INST: smlslb	z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0x50,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 50 df 44 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+smlslb   z21.d, z10.s, z5.s[1]
+// CHECK-INST: smlslb   z21.d, z10.s, z5.s[1]
+// CHECK-ENCODING: [0x55,0xa9,0xe5,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 55 a9 e5 44 <unknown>
diff --git a/test/MC/AArch64/SVE2/smlslt-diagnostics.s b/test/MC/AArch64/SVE2/smlslt-diagnostics.s
new file mode 100644
index 00000000000..81ababc5a4c
--- /dev/null
+++ b/test/MC/AArch64/SVE2/smlslt-diagnostics.s
@@ -0,0 +1,116 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+smlslt z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlslt z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.d, z1.s, z16.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smlslt z0.d, z1.s, z16.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+smlslt z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlslt z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: smlslt z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.d, z1.s, z15.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: smlslt z0.d, z1.s, z15.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.d, z1.s, z15.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: smlslt z0.d, z1.s, z15.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+smlslt z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.b, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.b, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.h, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.h, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.d, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.d, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.d, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.d, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smlslt z0.d, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smlslt z0.d, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+smlslt  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: smlslt  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.d, p0/z, z7.d
+smlslt  z0.d, z1.s, z15.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: smlslt  z0.d, z1.s, z15.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/test/MC/AArch64/SVE2/smlslt.s b/test/MC/AArch64/SVE2/smlslt.s
new file mode 100644
index 00000000000..b0bc1641818
--- /dev/null
+++ b/test/MC/AArch64/SVE2/smlslt.s
@@ -0,0 +1,67 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+smlslt z0.h, z1.b, z31.b
+// CHECK-INST: smlslt	z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x54,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 54 5f 44 <unknown>
+
+smlslt z0.s, z1.h, z31.h
+// CHECK-INST: smlslt	z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x54,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 54 9f 44 <unknown>
+
+smlslt z0.d, z1.s, z31.s
+// CHECK-INST: smlslt	z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x54,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 54 df 44 <unknown>
+
+smlslt z0.s, z1.h, z7.h[7]
+// CHECK-INST: smlslt	z0.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0xac,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 ac bf 44 <unknown>
+
+smlslt z0.d, z1.s, z15.s[1]
+// CHECK-INST: smlslt	z0.d, z1.s, z15.s[1]
+// CHECK-ENCODING: [0x20,0xac,0xef,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 ac ef 44 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+smlslt z21.d, z1.s, z31.s
+// CHECK-INST: smlslt	z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0x54,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 54 df 44 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+smlslt   z21.d, z10.s, z5.s[1]
+// CHECK-INST: smlslt   z21.d, z10.s, z5.s[1]
+// CHECK-ENCODING: [0x55,0xad,0xe5,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 55 ad e5 44 <unknown>
diff --git a/test/MC/AArch64/SVE2/umlalb-diagnostics.s b/test/MC/AArch64/SVE2/umlalb-diagnostics.s
new file mode 100644
index 00000000000..2da7cd45b36
--- /dev/null
+++ b/test/MC/AArch64/SVE2/umlalb-diagnostics.s
@@ -0,0 +1,116 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+umlalb z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlalb z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.d, z1.s, z16.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlalb z0.d, z1.s, z16.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+umlalb z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlalb z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlalb z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.d, z1.s, z15.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: umlalb z0.d, z1.s, z15.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.d, z1.s, z15.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: umlalb z0.d, z1.s, z15.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+umlalb z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.b, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.b, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.h, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.h, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.d, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.d, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.d, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.d, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalb z0.d, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalb z0.d, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+umlalb  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: umlalb  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.d, p0/z, z7.d
+umlalb  z0.d, z1.s, z15.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: umlalb  z0.d, z1.s, z15.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/test/MC/AArch64/SVE2/umlalb.s b/test/MC/AArch64/SVE2/umlalb.s
new file mode 100644
index 00000000000..4dcbe876854
--- /dev/null
+++ b/test/MC/AArch64/SVE2/umlalb.s
@@ -0,0 +1,67 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+umlalb z0.h, z1.b, z31.b
+// CHECK-INST: umlalb	z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x48,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 48 5f 44 <unknown>
+
+umlalb z0.s, z1.h, z31.h
+// CHECK-INST: umlalb	z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x48,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 48 9f 44 <unknown>
+
+umlalb z0.d, z1.s, z31.s
+// CHECK-INST: umlalb	z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x48,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 48 df 44 <unknown>
+
+umlalb z0.s, z1.h, z7.h[7]
+// CHECK-INST: umlalb	z0.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0x98,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 98 bf 44 <unknown>
+
+umlalb z0.d, z1.s, z15.s[1]
+// CHECK-INST: umlalb	z0.d, z1.s, z15.s[1]
+// CHECK-ENCODING: [0x20,0x98,0xef,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 98 ef 44 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+umlalb z21.d, z1.s, z31.s
+// CHECK-INST: umlalb	z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0x48,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 48 df 44 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+umlalb   z21.d, z10.s, z5.s[1]
+// CHECK-INST: umlalb   z21.d, z10.s, z5.s[1]
+// CHECK-ENCODING: [0x55,0x99,0xe5,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 55 99 e5 44 <unknown>
diff --git a/test/MC/AArch64/SVE2/umlalt-diagnostics.s b/test/MC/AArch64/SVE2/umlalt-diagnostics.s
new file mode 100644
index 00000000000..4cef711d141
--- /dev/null
+++ b/test/MC/AArch64/SVE2/umlalt-diagnostics.s
@@ -0,0 +1,116 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+umlalt z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlalt z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.d, z1.s, z16.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlalt z0.d, z1.s, z16.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+umlalt z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlalt z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlalt z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.d, z1.s, z15.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: umlalt z0.d, z1.s, z15.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.d, z1.s, z15.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: umlalt z0.d, z1.s, z15.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+umlalt z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.b, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.b, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.h, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.h, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.d, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.d, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.d, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.d, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlalt z0.d, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlalt z0.d, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+umlalt  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: umlalt  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.d, p0/z, z7.d
+umlalt  z0.d, z1.s, z15.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: umlalt  z0.d, z1.s, z15.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/test/MC/AArch64/SVE2/umlalt.s b/test/MC/AArch64/SVE2/umlalt.s
new file mode 100644
index 00000000000..9a8573f7b8d
--- /dev/null
+++ b/test/MC/AArch64/SVE2/umlalt.s
@@ -0,0 +1,67 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+umlalt z0.h, z1.b, z31.b
+// CHECK-INST: umlalt	z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x4c,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 4c 5f 44 <unknown>
+
+umlalt z0.s, z1.h, z31.h
+// CHECK-INST: umlalt	z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x4c,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 4c 9f 44 <unknown>
+
+umlalt z0.d, z1.s, z31.s
+// CHECK-INST: umlalt	z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x4c,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 4c df 44 <unknown>
+
+umlalt z0.s, z1.h, z7.h[7]
+// CHECK-INST: umlalt	z0.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0x9c,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 9c bf 44 <unknown>
+
+umlalt z0.d, z1.s, z15.s[1]
+// CHECK-INST: umlalt	z0.d, z1.s, z15.s[1]
+// CHECK-ENCODING: [0x20,0x9c,0xef,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 9c ef 44 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+umlalt z21.d, z1.s, z31.s
+// CHECK-INST: umlalt	z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0x4c,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 4c df 44 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+umlalt   z21.d, z10.s, z5.s[1]
+// CHECK-INST: umlalt   z21.d, z10.s, z5.s[1]
+// CHECK-ENCODING: [0x55,0x9d,0xe5,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 55 9d e5 44 <unknown>
diff --git a/test/MC/AArch64/SVE2/umlslb-diagnostics.s b/test/MC/AArch64/SVE2/umlslb-diagnostics.s
new file mode 100644
index 00000000000..f3570a191cb
--- /dev/null
+++ b/test/MC/AArch64/SVE2/umlslb-diagnostics.s
@@ -0,0 +1,116 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+umlslb z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlslb z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.d, z1.s, z16.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlslb z0.d, z1.s, z16.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+umlslb z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlslb z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlslb z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.d, z1.s, z15.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: umlslb z0.d, z1.s, z15.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.d, z1.s, z15.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: umlslb z0.d, z1.s, z15.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+umlslb z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.b, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.b, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.h, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.h, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.d, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.d, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.d, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.d, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslb z0.d, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslb z0.d, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+umlslb  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: umlslb  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.d, p0/z, z7.d
+umlslb  z0.d, z1.s, z15.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: umlslb  z0.d, z1.s, z15.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/test/MC/AArch64/SVE2/umlslb.s b/test/MC/AArch64/SVE2/umlslb.s
new file mode 100644
index 00000000000..194a2c1fae1
--- /dev/null
+++ b/test/MC/AArch64/SVE2/umlslb.s
@@ -0,0 +1,67 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+umlslb z0.h, z1.b, z31.b
+// CHECK-INST: umlslb	z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x58,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 58 5f 44 <unknown>
+
+umlslb z0.s, z1.h, z31.h
+// CHECK-INST: umlslb	z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x58,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 58 9f 44 <unknown>
+
+umlslb z0.d, z1.s, z31.s
+// CHECK-INST: umlslb	z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x58,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 58 df 44 <unknown>
+
+umlslb z0.s, z1.h, z7.h[7]
+// CHECK-INST: umlslb	z0.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0xb8,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 b8 bf 44 <unknown>
+
+umlslb z0.d, z1.s, z15.s[1]
+// CHECK-INST: umlslb	z0.d, z1.s, z15.s[1]
+// CHECK-ENCODING: [0x20,0xb8,0xef,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 b8 ef 44 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+umlslb z21.d, z1.s, z31.s
+// CHECK-INST: umlslb	z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0x58,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 58 df 44 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+umlslb   z21.d, z10.s, z5.s[1]
+// CHECK-INST: umlslb   z21.d, z10.s, z5.s[1]
+// CHECK-ENCODING: [0x55,0xb9,0xe5,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 55 b9 e5 44 <unknown>
diff --git a/test/MC/AArch64/SVE2/umlslt-diagnostics.s b/test/MC/AArch64/SVE2/umlslt-diagnostics.s
new file mode 100644
index 00000000000..074e5fb5938
--- /dev/null
+++ b/test/MC/AArch64/SVE2/umlslt-diagnostics.s
@@ -0,0 +1,116 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// z register out of range for index
+
+umlslt z0.s, z1.h, z8.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlslt z0.s, z1.h, z8.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.d, z1.s, z16.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umlslt z0.d, z1.s, z16.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Index out of bounds
+
+umlslt z0.s, z1.h, z7.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlslt z0.s, z1.h, z7.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.s, z1.h, z7.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: umlslt z0.s, z1.h, z7.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.d, z1.s, z15.s[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: umlslt z0.d, z1.s, z15.s[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.d, z1.s, z15.s[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: umlslt z0.d, z1.s, z15.s[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+umlslt z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.b, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.b, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.h, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.h, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.s, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.s, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.s, z1.s, z2.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.s, z1.s, z2.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.s, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.s, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.d, z1.b, z2.b[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.d, z1.b, z2.b[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.d, z1.h, z2.h[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.d, z1.h, z2.h[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umlslt z0.d, z1.d, z2.d[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umlslt z0.d, z1.d, z2.d[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+umlslt  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: umlslt  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.d, p0/z, z7.d
+umlslt  z0.d, z1.s, z15.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: umlslt  z0.d, z1.s, z15.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/test/MC/AArch64/SVE2/umlslt.s b/test/MC/AArch64/SVE2/umlslt.s
new file mode 100644
index 00000000000..24e7f4fe8a1
--- /dev/null
+++ b/test/MC/AArch64/SVE2/umlslt.s
@@ -0,0 +1,67 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+umlslt z0.h, z1.b, z31.b
+// CHECK-INST: umlslt	z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x5c,0x5f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 5c 5f 44 <unknown>
+
+umlslt z0.s, z1.h, z31.h
+// CHECK-INST: umlslt	z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x5c,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 5c 9f 44 <unknown>
+
+umlslt z0.d, z1.s, z31.s
+// CHECK-INST: umlslt	z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0x5c,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 5c df 44 <unknown>
+
+umlslt z0.s, z1.h, z7.h[7]
+// CHECK-INST: umlslt	z0.s, z1.h, z7.h[7]
+// CHECK-ENCODING: [0x20,0xbc,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 bc bf 44 <unknown>
+
+umlslt z0.d, z1.s, z15.s[1]
+// CHECK-INST: umlslt	z0.d, z1.s, z15.s[1]
+// CHECK-ENCODING: [0x20,0xbc,0xef,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 bc ef 44 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+umlslt z21.d, z1.s, z31.s
+// CHECK-INST: umlslt	z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0x5c,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 5c df 44 <unknown>
+
+movprfx z21, z28
+// CHECK-INST: movprfx	z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+umlslt   z21.d, z10.s, z5.s[1]
+// CHECK-INST: umlslt   z21.d, z10.s, z5.s[1]
+// CHECK-ENCODING: [0x55,0xbd,0xe5,0x44]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 55 bd e5 44 <unknown>