From: Sanjay Patel Date: Fri, 23 Jun 2017 15:29:49 +0000 (+0000) Subject: [x86] auto-generate complete checks; NFC X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=45dca99e22e95666bfcc4d500b58c1b1684abd32;p=llvm [x86] auto-generate complete checks; NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306114 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/X86/machine-cse.ll b/test/CodeGen/X86/machine-cse.ll index 9853a7cde67..abf39c9a058 100644 --- a/test/CodeGen/X86/machine-cse.ll +++ b/test/CodeGen/X86/machine-cse.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=x86_64-apple-macosx < %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s ; rdar://7610418 %ptr = type { i8* } @@ -7,26 +8,30 @@ %struct.s3 = type { %struct.s3*, %struct.s3*, i32, i32, i32 } define fastcc i8* @t(i32 %base) nounwind { -entry: ; CHECK-LABEL: t: -; CHECK: leaq (%rax,%rax,4) +; CHECK: # BB#0: # %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: shlq $9, %rax +; CHECK-NEXT: leaq (%rax,%rax,4), %rdi +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: testb %al, %al +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: callq bar +; CHECK-NEXT: .LBB0_2: # %bb2 +; CHECK-NEXT: callq foo +entry: %0 = zext i32 %base to i64 %1 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0 br i1 undef, label %bb1, label %bb2 bb1: -; CHECK: %bb1 -; CHECK-NOT: shlq $9 -; CHECK-NOT: leaq -; CHECK: call %2 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0, i32 0 call void @bar(i32* %2) nounwind unreachable bb2: -; CHECK: %bb2 -; CHECK-NOT: leaq -; CHECK: callq %3 = call fastcc i8* @foo(%struct.s2* %1) nounwind unreachable @@ -44,6 +49,30 @@ declare void @printf(...) nounwind define void @commute(i32 %test_case, i32 %scale) nounwind ssp { ; CHECK-LABEL: commute: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: # kill: %ESI %ESI %RSI +; CHECK-NEXT: # kill: %EDI %EDI %RDI +; CHECK-NEXT: leal -1(%rdi), %eax +; CHECK-NEXT: cmpl $2, %eax +; CHECK-NEXT: ja .LBB1_4 +; CHECK-NEXT: # BB#1: # %sw.bb +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: testb %al, %al +; CHECK-NEXT: jne .LBB1_4 +; CHECK-NEXT: # BB#2: # %if.end34 +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: imull %edi, %esi +; CHECK-NEXT: leal (%rsi,%rsi,2), %esi +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: # kill: %EDI %EDI %RDI +; CHECK-NEXT: callq printf +; CHECK-NEXT: addq $8, %rsp +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB1_3: # %for.body53.us +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: jmp .LBB1_3 +; CHECK-NEXT: .LBB1_4: # %sw.bb307 +; CHECK-NEXT: retq entry: switch i32 %test_case, label %sw.bb307 [ i32 1, label %sw.bb @@ -51,67 +80,78 @@ entry: i32 3, label %sw.bb ] -sw.bb: ; preds = %entry, %entry, %entry -; CHECK: %sw.bb -; CHECK-NOT: imull +sw.bb: %mul = mul nsw i32 %test_case, 3 %mul20 = mul nsw i32 %mul, %scale br i1 undef, label %if.end34, label %sw.bb307 -if.end34: ; preds = %sw.bb -; CHECK: %if.end34 -; CHECK: imull -; CHECK: leal +if.end34: tail call void (...) @printf(i32 %test_case, i32 %mul20) nounwind %tmp = mul i32 %scale, %test_case %tmp752 = mul i32 %tmp, 3 %tmp753 = zext i32 %tmp752 to i64 br label %bb.nph743.us -for.body53.us: ; preds = %bb.nph743.us, %for.body53.us +for.body53.us: %exitcond = icmp eq i64 undef, %tmp753 br i1 %exitcond, label %bb.nph743.us, label %for.body53.us -bb.nph743.us: ; preds = %for.body53.us, %if.end34 +bb.nph743.us: br label %for.body53.us -sw.bb307: ; preds = %sw.bb, %entry +sw.bb307: ret void } ; CSE physical register defining instruction across MBB boundary. ; rdar://10660865 define i32 @cross_mbb_phys_cse(i32 %a, i32 %b) nounwind ssp { -entry: ; CHECK-LABEL: cross_mbb_phys_cse: -; CHECK: cmpl -; CHECK: ja +; CHECK: # BB#0: # %entry +; CHECK-NEXT: movl $1, %eax +; CHECK-NEXT: cmpl %esi, %edi +; CHECK-NEXT: ja .LBB2_2 +; CHECK-NEXT: # BB#1: # %if.end +; CHECK-NEXT: sbbl %eax, %eax +; CHECK-NEXT: .LBB2_2: # %return +; CHECK-NEXT: retq +entry: %cmp = icmp ugt i32 %a, %b br i1 %cmp, label %return, label %if.end -if.end: ; preds = %entry -; CHECK-NOT: cmpl -; CHECK: sbbl +if.end: %cmp1 = icmp ult i32 %a, %b %. = sext i1 %cmp1 to i32 br label %return -return: ; preds = %if.end, %entry +return: %retval.0 = phi i32 [ 1, %entry ], [ %., %if.end ] ret i32 %retval.0 } ; rdar://11393714 define i8* @bsd_memchr(i8* %s, i32 %a, i32 %c, i64 %n) nounwind ssp { -; CHECK: %entry -; CHECK-NOT: xorl -; CHECK: %preheader -; CHECK-NOT: xorl -; CHECK: %do.body -; CHECK-NOT: xorl -; CHECK: %do.cond -; CHECK: xorl -; CHECK: %return +; CHECK-LABEL: bsd_memchr: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: testq %rcx, %rcx +; CHECK-NEXT: je .LBB3_4 +; CHECK-NEXT: # BB#1: # %preheader +; CHECK-NEXT: movzbl %dl, %eax +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB3_2: # %do.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: cmpl %eax, %esi +; CHECK-NEXT: je .LBB3_5 +; CHECK-NEXT: # BB#3: # %do.cond +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: incq %rdi +; CHECK-NEXT: decq %rcx +; CHECK-NEXT: jne .LBB3_2 +; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: xorl %edi, %edi +; CHECK-NEXT: .LBB3_5: # %return +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq entry: %cmp = icmp eq i64 %n, 0 br i1 %cmp, label %return, label %preheader @@ -142,7 +182,22 @@ return: declare i1 @t2_func() -define i32 @t2() { +define i32 @t2() nounwind { +; CHECK-LABEL: t2: +; CHECK: # BB#0: +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: movl $42, {{.*}}(%rip) +; CHECK-NEXT: callq t2_func +; CHECK-NEXT: testb $1, %al +; CHECK-NEXT: je .LBB4_2 +; CHECK-NEXT: # BB#1: # %a +; CHECK-NEXT: movl {{.*}}(%rip), %eax +; CHECK-NEXT: popq %rcx +; CHECK-NEXT: retq +; CHECK-NEXT: .LBB4_2: # %b +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: popq %rcx +; CHECK-NEXT: retq store i32 42, i32* @t2_global %c = call i1 @t2_func() br i1 %c, label %a, label %b @@ -153,8 +208,5 @@ a: b: ret i32 0 - -; CHECK-LABEL: t2: -; CHECK: t2_global@GOTPCREL(%rip) -; CHECK-NOT: t2_global@GOTPCREL(%rip) } +