From: Matt Arsenault Date: Sat, 18 Feb 2017 18:41:41 +0000 (+0000) Subject: AMDGPU: Fix disassembly of aperture registers X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=4371ec2c187403e68f2e4ce46b264865d057a489;p=llvm AMDGPU: Fix disassembly of aperture registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295555 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 5733b9cace1..ff95a9b23af 100644 --- a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -523,6 +523,11 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { case 124: return createRegOperand(M0); case 126: return createRegOperand(EXEC_LO); case 127: return createRegOperand(EXEC_HI); + case 235: return createRegOperand(SRC_SHARED_BASE); + case 236: return createRegOperand(SRC_SHARED_LIMIT); + case 237: return createRegOperand(SRC_PRIVATE_BASE); + case 238: return createRegOperand(SRC_PRIVATE_LIMIT); + // TODO: SRC_POPS_EXITING_WAVE_ID // ToDo: no support for vccz register case 251: break; // ToDo: no support for execz register diff --git a/test/MC/Disassembler/AMDGPU/aperture-regs.ll b/test/MC/Disassembler/AMDGPU/aperture-regs.ll new file mode 100644 index 00000000000..5fec281145b --- /dev/null +++ b/test/MC/Disassembler/AMDGPU/aperture-regs.ll @@ -0,0 +1,13 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX9 %s + +# GFX9: v_mov_b32_e32 v1, src_shared_base ; encoding: [0xeb,0x02,0x02,0x7e] +0xeb 0x02 0x02 0x7e + +# GFX9: v_mov_b32_e32 v1, src_shared_limit ; encoding: [0xec,0x02,0x02,0x7e] +0xec 0x02 0x02 0x7e + +# GFX9: v_mov_b32_e32 v1, src_private_base ; encoding: [0xed,0x02,0x02,0x7e] +0xed 0x02 0x02 0x7e + +# GFX9: v_mov_b32_e32 v1, src_private_limit ; encoding: [0xee,0x02,0x02,0x7e] +0xee 0x02 0x02 0x7e