From: Simon Pilgrim Date: Fri, 20 Jul 2018 15:51:01 +0000 (+0000) Subject: [X86][AVX] Add support for i16 256-bit vector horizontal op redundant shuffle removal X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=42411242d60a9378f1c2d634c330a033550374e8;p=llvm [X86][AVX] Add support for i16 256-bit vector horizontal op redundant shuffle removal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337566 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index e1b7adfaf50..3e57c3ca2d4 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -31164,7 +31164,9 @@ static SDValue foldShuffleOfHorizOp(SDNode *N) { if (HOp.getValueSizeInBits() == 256 && (isTargetShuffleEquivalent(Mask, {0, 0, 2, 2}) || - isTargetShuffleEquivalent(Mask, {0, 1, 0, 1, 4, 5, 4, 5}))) + isTargetShuffleEquivalent(Mask, {0, 1, 0, 1, 4, 5, 4, 5}) || + isTargetShuffleEquivalent( + Mask, {0, 1, 2, 3, 0, 1, 2, 3, 8, 9, 10, 11, 8, 9, 10, 11}))) return HOp; return SDValue(); diff --git a/test/CodeGen/X86/haddsub-shuf.ll b/test/CodeGen/X86/haddsub-shuf.ll index 935d3254d5c..1a602d1664b 100644 --- a/test/CodeGen/X86/haddsub-shuf.ll +++ b/test/CodeGen/X86/haddsub-shuf.ll @@ -432,7 +432,6 @@ define <16 x i16> @hadd_v16i16b(<16 x i16> %a) { ; AVX2-LABEL: hadd_v16i16b: ; AVX2: # %bb.0: ; AVX2-NEXT: vphaddw %ymm0, %ymm0, %ymm0 -; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5] ; AVX2-NEXT: retq %a0 = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> %a1 = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> @@ -513,7 +512,6 @@ define <16 x i16> @hsub_v16i16b(<16 x i16> %a) { ; AVX2-LABEL: hsub_v16i16b: ; AVX2: # %bb.0: ; AVX2-NEXT: vphsubw %ymm0, %ymm0, %ymm0 -; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5] ; AVX2-NEXT: retq %a0 = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> %a1 = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32>