From: Sander de Smalen Date: Wed, 18 Jul 2018 11:59:12 +0000 (+0000) Subject: [AArch64][SVE] Asm: Support for unpredicated FP operations. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=41ef3985c79e3151d917a2b590785dca9863d7ad;p=llvm [AArch64][SVE] Asm: Support for unpredicated FP operations. This patch adds support for the following unpredicated floating-point instructions: FADD Floating point add FSUB Floating point subtract FMUL Floating point multiplication FTSMUL Floating point trigonometric starting value FRECPS Floating point reciprocal step FRSQRTS Floating point reciprocal square root step The instructions have the following assembly format: fadd z0.h, z1.h, z2.h and have variants for 16, 32 and 64-bit FP elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337383 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index 94f0be01b3c..a5569d2ad61 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -125,6 +125,13 @@ let Predicates = [HasSVE] in { defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr">; defm FDIV_ZPmZ : sve_fp_2op_p_zds<0b1101, "fdiv">; + defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd">; + defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub">; + defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul">; + defm FTSMUL_ZZZ : sve_fp_3op_u_zd<0b011, "ftsmul">; + defm FRECPS_ZZZ : sve_fp_3op_u_zd<0b110, "frecps">; + defm FRSQRTS_ZZZ : sve_fp_3op_u_zd<0b111, "frsqrts">; + defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">; defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">; diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index 4bcde3edbcf..642e48f3063 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -986,6 +986,34 @@ multiclass sve_fp_2op_p_zds opc, string asm> { } +//===----------------------------------------------------------------------===// +// SVE Floating Point Arithmetic - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve_fp_3op_u_zd sz, bits<3> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b01100101; + let Inst{23-22} = sz; + let Inst{21} = 0b0; + let Inst{20-16} = Zm; + let Inst{15-13} = 0b000; + let Inst{12-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_fp_3op_u_zd opc, string asm> { + def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>; + def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>; + def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64>; +} + //===----------------------------------------------------------------------===// // SVE Floating Point Fused Multiply-Add Group //===----------------------------------------------------------------------===// diff --git a/test/MC/AArch64/SVE/fadd-diagnostics.s b/test/MC/AArch64/SVE/fadd-diagnostics.s index 587e03fdd85..be8a85fa49b 100644 --- a/test/MC/AArch64/SVE/fadd-diagnostics.s +++ b/test/MC/AArch64/SVE/fadd-diagnostics.s @@ -51,6 +51,15 @@ fadd z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fadd z0.h, p7/m, z0.h, z31.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +fadd z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fadd z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fadd z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fadd z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // ------------------------------------------------------------------------- // // Invalid predicate diff --git a/test/MC/AArch64/SVE/fadd.s b/test/MC/AArch64/SVE/fadd.s index 238305d993f..36c3171bba8 100644 --- a/test/MC/AArch64/SVE/fadd.s +++ b/test/MC/AArch64/SVE/fadd.s @@ -72,3 +72,21 @@ fadd z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c0 65 + +fadd z0.h, z1.h, z31.h +// CHECK-INST: fadd z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x00,0x5f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 5f 65 + +fadd z0.s, z1.s, z31.s +// CHECK-INST: fadd z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x00,0x9f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 9f 65 + +fadd z0.d, z1.d, z31.d +// CHECK-INST: fadd z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x00,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 00 df 65 diff --git a/test/MC/AArch64/SVE/fmul-diagnostics.s b/test/MC/AArch64/SVE/fmul-diagnostics.s index 2000b33df51..55bfbd7cef6 100644 --- a/test/MC/AArch64/SVE/fmul-diagnostics.s +++ b/test/MC/AArch64/SVE/fmul-diagnostics.s @@ -43,17 +43,17 @@ fmul z0.h, z0.h, z8.b[0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: fmul z0.h, z0.h, z8.h[0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fmul z0.h, z0.h, z8.h[0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: fmul z0.s, z0.s, z8.s[0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fmul z0.s, z0.s, z8.s[0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: fmul z0.d, z0.d, z16.d[0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fmul z0.d, z0.d, z16.d[0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -114,6 +114,16 @@ fmul z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fmul z0.h, p7/m, z0.h, z31.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +fmul z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmul z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmul z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmul z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + // ------------------------------------------------------------------------- // // Invalid predicate diff --git a/test/MC/AArch64/SVE/fmul.s b/test/MC/AArch64/SVE/fmul.s index 128be97e4c8..fd75166319b 100644 --- a/test/MC/AArch64/SVE/fmul.s +++ b/test/MC/AArch64/SVE/fmul.s @@ -102,3 +102,21 @@ fmul z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c2 65 + +fmul z0.h, z1.h, z31.h +// CHECK-INST: fmul z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x08,0x5f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 08 5f 65 + +fmul z0.s, z1.s, z31.s +// CHECK-INST: fmul z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x08,0x9f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 08 9f 65 + +fmul z0.d, z1.d, z31.d +// CHECK-INST: fmul z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x08,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 08 df 65 diff --git a/test/MC/AArch64/SVE/frecps-diagnostics.s b/test/MC/AArch64/SVE/frecps-diagnostics.s new file mode 100644 index 00000000000..7de58cff80f --- /dev/null +++ b/test/MC/AArch64/SVE/frecps-diagnostics.s @@ -0,0 +1,15 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element size + +frecps z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: frecps z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +frecps z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: frecps z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/frecps.s b/test/MC/AArch64/SVE/frecps.s new file mode 100644 index 00000000000..442cbd8f325 --- /dev/null +++ b/test/MC/AArch64/SVE/frecps.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +frecps z0.h, z1.h, z31.h +// CHECK-INST: frecps z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x18,0x5f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 18 5f 65 + +frecps z0.s, z1.s, z31.s +// CHECK-INST: frecps z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x18,0x9f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 18 9f 65 + +frecps z0.d, z1.d, z31.d +// CHECK-INST: frecps z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x18,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 18 df 65 diff --git a/test/MC/AArch64/SVE/frsqrts-diagnostics.s b/test/MC/AArch64/SVE/frsqrts-diagnostics.s new file mode 100644 index 00000000000..07dde46ad45 --- /dev/null +++ b/test/MC/AArch64/SVE/frsqrts-diagnostics.s @@ -0,0 +1,15 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element size + +frsqrts z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: frsqrts z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +frsqrts z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: frsqrts z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/frsqrts.s b/test/MC/AArch64/SVE/frsqrts.s new file mode 100644 index 00000000000..ac61e882f70 --- /dev/null +++ b/test/MC/AArch64/SVE/frsqrts.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +frsqrts z0.h, z1.h, z31.h +// CHECK-INST: frsqrts z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x1c,0x5f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c 5f 65 + +frsqrts z0.s, z1.s, z31.s +// CHECK-INST: frsqrts z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x1c,0x9f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c 9f 65 + +frsqrts z0.d, z1.d, z31.d +// CHECK-INST: frsqrts z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x1c,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 1c df 65 diff --git a/test/MC/AArch64/SVE/fsub-diagnostics.s b/test/MC/AArch64/SVE/fsub-diagnostics.s index a67d6782905..27d1b3f7b91 100644 --- a/test/MC/AArch64/SVE/fsub-diagnostics.s +++ b/test/MC/AArch64/SVE/fsub-diagnostics.s @@ -51,6 +51,15 @@ fsub z0.h, p7/m, z0.h, z31.s // CHECK-NEXT: fsub z0.h, p7/m, z0.h, z31.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +fsub z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fsub z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fsub z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fsub z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // ------------------------------------------------------------------------- // // Invalid predicate diff --git a/test/MC/AArch64/SVE/fsub.s b/test/MC/AArch64/SVE/fsub.s index 7172c31aa6b..8e96cbb65ad 100644 --- a/test/MC/AArch64/SVE/fsub.s +++ b/test/MC/AArch64/SVE/fsub.s @@ -72,3 +72,21 @@ fsub z0.d, p7/m, z0.d, z31.d // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: e0 9f c1 65 + +fsub z0.h, z1.h, z31.h +// CHECK-INST: fsub z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x04,0x5f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 5f 65 + +fsub z0.s, z1.s, z31.s +// CHECK-INST: fsub z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x04,0x9f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 9f 65 + +fsub z0.d, z1.d, z31.d +// CHECK-INST: fsub z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x04,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 04 df 65 diff --git a/test/MC/AArch64/SVE/ftsmul-diagnostics.s b/test/MC/AArch64/SVE/ftsmul-diagnostics.s new file mode 100644 index 00000000000..5ad0a14d798 --- /dev/null +++ b/test/MC/AArch64/SVE/ftsmul-diagnostics.s @@ -0,0 +1,15 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element size + +ftsmul z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ftsmul z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ftsmul z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ftsmul z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ftsmul.s b/test/MC/AArch64/SVE/ftsmul.s new file mode 100644 index 00000000000..1b41fca7c2b --- /dev/null +++ b/test/MC/AArch64/SVE/ftsmul.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ftsmul z0.h, z1.h, z31.h +// CHECK-INST: ftsmul z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x0c,0x5f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 0c 5f 65 + +ftsmul z0.s, z1.s, z31.s +// CHECK-INST: ftsmul z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x0c,0x9f,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 0c 9f 65 + +ftsmul z0.d, z1.d, z31.d +// CHECK-INST: ftsmul z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x0c,0xdf,0x65] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 0c df 65