From: Asaf Badouh <asaf.badouh@intel.com>
Date: Thu, 1 Dec 2016 15:19:10 +0000 (+0000)
Subject: [LMT] Restrict nop length to one
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=400d54c2399c928f84664afd612e0caabce58232;p=llvm

[LMT] Restrict nop length to one
not all lakemont MCU support long nop.
we can't assume we can generate long nop by default for MCU.

Differential Revision: https://reviews.llvm.org/D26895

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288363 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index 1bde4bcfa29..e83ec9f4045 100644
--- a/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -76,12 +76,12 @@ class X86AsmBackend : public MCAsmBackend {
 public:
   X86AsmBackend(const Target &T, StringRef CPU)
       : MCAsmBackend(), CPU(CPU),
-        MaxNopLength((CPU == "slm" || CPU == "lakemont") ? 7 : 15) {
+        MaxNopLength((CPU == "slm") ? 7 : 15) {
     HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
               CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
               CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
               CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
-              CPU != "c3" && CPU != "c3-2";
+              CPU != "c3" && CPU != "c3-2" && CPU != "lakemont";
   }
 
   unsigned getNumFixupKinds() const override {
diff --git a/test/MC/X86/x86_long_nop.s b/test/MC/X86/x86_long_nop.s
index 806f841e891..0657ece18b7 100644
--- a/test/MC/X86/x86_long_nop.s
+++ b/test/MC/X86/x86_long_nop.s
@@ -3,7 +3,7 @@
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
-# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
+# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=NOP1 %s
 
 # Ensure alignment directives also emit sequences of 15-byte NOPs on processors
 # capable of using long NOPs.
@@ -16,8 +16,7 @@ inc %eax
 # CHECK-NEXT: 1f:  nop
 # CHECK-NEXT: 20:  inc
 
-# On Silvermont and Lakemont we emit only 7 byte NOPs since longer NOPs
-# are not profitable.
+# On Silvermont we emit only 7 byte NOPs since longer NOPs are not profitable.
 # LNOP7: 0:  inc
 # LNOP7-NEXT: 1:  nop
 # LNOP7-NEXT: 8:  nop
@@ -25,3 +24,23 @@ inc %eax
 # LNOP7-NEXT: 16:  nop
 # LNOP7-NEXT: 1d:  nop
 # LNOP7-NEXT: 20:  inc
+
+# On Lakemont we emit only 1 byte NOPs since longer NOPs are not supported/legal
+# NOP1: 0:  inc
+# NOP1-NEXT: 1:  nop
+# NOP1-NEXT: 2:  nop
+# NOP1-NEXT: 3:  nop
+# NOP1-NEXT: 4:  nop
+# NOP1-NEXT: 5:  nop
+# NOP1-NEXT: 6:  nop
+# .......
+# NOP1: 17:  nop
+# NOP1-NEXT: 18:  nop
+# NOP1-NEXT: 19:  nop
+# NOP1-NEXT: 1a:  nop
+# NOP1-NEXT: 1b:  nop
+# NOP1-NEXT: 1c:  nop
+# NOP1-NEXT: 1d:  nop
+# NOP1-NEXT: 1e:  nop
+# NOP1-NEXT: 1f:  nop
+# NOP1-NEXT: 20:  inc