From: Pekka Jaaskelainen Date: Tue, 27 Jan 2015 10:23:05 +0000 (+0000) Subject: pocl and TCE work with LLVM 3.6 now. Added them to the ReleaseNotes. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=3fdca844a0abfbd6b1b84031770f44b5f8332357;p=llvm pocl and TCE work with LLVM 3.6 now. Added them to the ReleaseNotes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@227188 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index 8e726a1bd15..f27fb027708 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -513,8 +513,35 @@ An exciting aspect of LLVM is that it is used as an enabling technology for a lot of other language and tools projects. This section lists some of the projects that have already been updated to work with LLVM 3.6. -* A project +Portable Computing Language (pocl) +---------------------------------- +In addition to producing an easily portable open source OpenCL +implementation, another major goal of `pocl `_ +is improving performance portability of OpenCL programs with +compiler optimizations, reducing the need for target-dependent manual +optimizations. An important part of pocl is a set of LLVM passes used to +statically parallelize multiple work-items with the kernel compiler, even in +the presence of work-group barriers. This enables static parallelization of +the fine-grained static concurrency in the work groups in multiple ways. + +TTA-based Co-design Environment (TCE) +------------------------------------- + +`TCE `_ is a toolset for designing customized +exposed datapath processors based on the Transport triggered +architecture (TTA). + +The toolset provides a complete co-design flow from C/C++ +programs down to synthesizable VHDL/Verilog and parallel program binaries. +Processor customization points include the register files, function units, +supported operations, and the interconnection network. + +TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent +optimizations and also for parts of code generation. It generates +new LLVM-based code generators "on the fly" for the designed processors and +loads them in to the compiler backend as runtime libraries to avoid +per-target recompilation of larger parts of the compiler chain. Additional Information ======================