From: Sanjay Patel <spatel@rotateright.com>
Date: Fri, 28 Oct 2016 19:08:20 +0000 (+0000)
Subject: [x86] add tests for missed umin/umax
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=3dc20a0272db4bc226e095192316c3109ba54b0e;p=llvm

[x86] add tests for missed umin/umax

This is actually a deficiency in ValueTracking's matchSelectPattern(),
but a codegen test is the simplest way to expose the bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285429 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/vec_umin_umax.ll b/test/CodeGen/X86/vec_umin_umax.ll
new file mode 100644
index 00000000000..a3354eb69b8
--- /dev/null
+++ b/test/CodeGen/X86/vec_umin_umax.ll
@@ -0,0 +1,59 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
+
+; FIXME: These are unsigned min/max ops.
+
+define <4 x i32> @umax_vec1(<4 x i32> %x) {
+; CHECK-LABEL: umax_vec1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT:    vpcmpgtd %xmm0, %xmm1, %xmm1
+; CHECK-NEXT:    vmovaps {{.*#+}} xmm2 = [2147483647,2147483647,2147483647,2147483647]
+; CHECK-NEXT:    vblendvps %xmm1, %xmm0, %xmm2, %xmm0
+; CHECK-NEXT:    retq
+;
+  %cmp = icmp slt <4 x i32> %x, zeroinitializer
+  %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+  ret <4 x i32> %sel
+}
+
+define <4 x i32> @umax_vec2(<4 x i32> %x) {
+; CHECK-LABEL: umax_vec2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT:    vpcmpgtd %xmm1, %xmm0, %xmm1
+; CHECK-NEXT:    vblendvps %xmm1, {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    retq
+;
+  %cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>, <4 x i32> %x
+  ret <4 x i32> %sel
+}
+
+define <4 x i32> @umin_vec1(<4 x i32> %x) {
+; CHECK-LABEL: umin_vec1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT:    vpcmpgtd %xmm0, %xmm1, %xmm1
+; CHECK-NEXT:    vblendvps %xmm1, {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    retq
+;
+  %cmp = icmp slt <4 x i32> %x, zeroinitializer
+  %sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %x
+  ret <4 x i32> %sel
+}
+
+define <4 x i32> @umin_vec2(<4 x i32> %x) {
+; CHECK-LABEL: umin_vec2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT:    vpcmpgtd %xmm1, %xmm0, %xmm1
+; CHECK-NEXT:    vmovaps {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; CHECK-NEXT:    vblendvps %xmm1, %xmm0, %xmm2, %xmm0
+; CHECK-NEXT:    retq
+;
+  %cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
+  ret <4 x i32> %sel
+}
+