From: Craig Topper <craig.topper@intel.com>
Date: Sun, 10 Mar 2019 17:20:42 +0000 (+0000)
Subject: [X86] Remove dead code from the handler for INTR_TYPE_SCALAR_MASK_RM.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=3d8d3321c08b34638ff5b7440f09138a0b4de971;p=llvm

[X86] Remove dead code from the handler for INTR_TYPE_SCALAR_MASK_RM.

The code in here handles nodes with 6 or 7 operands. But only the 6 operand case is ever used these days.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355788 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 863b93ee6b9..7d3bdaf9f57 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -22026,24 +22026,14 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                   Mask, passThru, Subtarget, DAG);
     }
     case INTR_TYPE_SCALAR_MASK_RM: {
+      assert(Op.getNumOperands() == 6 && "Unexpected number of operands");
       SDValue Src1 = Op.getOperand(1);
       SDValue Src2 = Op.getOperand(2);
       SDValue Src0 = Op.getOperand(3);
       SDValue Mask = Op.getOperand(4);
-      // There are 2 kinds of intrinsics in this group:
-      // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
-      // (2) With rounding mode and sae - 7 operands.
-      if (Op.getNumOperands() == 6) {
-        SDValue Sae  = Op.getOperand(5);
-        return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
-                                                Sae),
-                                    Mask, Src0, Subtarget, DAG);
-      }
-      assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
-      SDValue RoundingMode  = Op.getOperand(5);
-      SDValue Sae  = Op.getOperand(6);
+      SDValue Rnd  = Op.getOperand(5);
       return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
-                                              RoundingMode, Sae),
+                                              Rnd),
                                   Mask, Src0, Subtarget, DAG);
     }
     case INTR_TYPE_2OP_MASK: {