From: Zoltan Varga <vargaz@gmail.com>
Date: Fri, 5 Mar 2010 14:22:32 +0000 (+0000)
Subject: In libgc/:
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=3c9f632c47f221a501a43305fb6db13971182c00;p=gc

In libgc/:

2010-03-04  David S. Miller  <davem@davemloft.net>

       * include/private/gc_locks.h: Add SPARC implementations of
       GC_compare_and_exchange and GC_memory_barrier.

In mono/mini/:

2010-03-04  David S. Miller  <davem@davemloft.net>

       * mini-sparc.h: Always use MONO_ARCH_USE_SIGACTION.  Linux kernels
       that don't provide the siginfo in the second signal handler argument
       are buggy, and this has been fixed for years.
       * mini.h (GET_CONTEXT): Remove __sparc__ special case.
       (SIG_HANDLER_SIGNATURE, SIG_HANDLER_PARMS): Likewise.

svn path=/trunk/mono/; revision=153114
---

diff --git a/ChangeLog b/ChangeLog
index 0dcfc7e5..5734f44a 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2010-03-04  David S. Miller  <davem@davemloft.net>
+
+       * include/private/gc_locks.h: Add SPARC implementations of
+       GC_compare_and_exchange and GC_memory_barrier.
+
 2010-02-22  Zoltan Varga  <vargaz@gmail.com>
 
 	* obj_map.c (GC_add_map_entry): Speed this up for the common case where
diff --git a/include/private/gc_locks.h b/include/private/gc_locks.h
index 23a506a9..3803f6ac 100644
--- a/include/private/gc_locks.h
+++ b/include/private/gc_locks.h
@@ -500,6 +500,51 @@
         }
 #     endif /* POWERPC */
 
+#     if defined(SPARC)
+#      if !defined(GENERIC_COMPARE_AND_SWAP)
+#       if CPP_WORDSZ == 64
+        /* Returns TRUE if the comparison succeeded. */
+        inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
+            GC_word old, GC_word new_val)
+        {
+            unsigned long result;
+            __asm__ __volatile__(
+               "casx [%2], %3, %0"
+                :  "=r" (result)
+                :  "0" (new_val), "r" (addr), "r" (old)
+                : "memory");
+            return (GC_bool) (result == old);
+        }
+#       else
+        /* Returns TRUE if the comparison succeeded. */
+        inline static GC_bool GC_compare_and_exchange(volatile GC_word *_addr,
+            GC_word _old, GC_word _new_val)
+        {
+           register unsigned long result asm("o0");
+           register unsigned long old asm("o1");
+           register volatile GC_word *addr asm("o2");
+           result = _new_val;
+           old = _old;
+           addr = _addr;
+            __asm__ __volatile__(
+               /* We encode the instruction directly so that it
+                  doesn't taint the whole binary as v9-only.  */
+               ".word 0xd1e29009" /* cas [%o2], %o1, %o0 */
+                :  "=r" (result)
+                :  "0" (result), "r" (addr), "r"(old)
+                : "memory");
+            return (GC_bool) (result == old);
+        }
+#       endif
+#      endif /* !GENERIC_COMPARE_AND_SWAP */
+        inline static void GC_memory_barrier()
+        {
+           /* All sparc v9 chips provice procesor consistent ordering. */
+           /* Thus a compiler barrier should suffice.                  */
+            __asm__ __volatile__("" : : : "memory");
+        }
+#     endif /* SPARC */
+
 #     if defined(IA64)
 #      if !defined(GENERIC_COMPARE_AND_SWAP)
          inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,