From: Artem Tamazov Date: Fri, 6 May 2016 19:32:38 +0000 (+0000) Subject: [AMDGPU][llvm-mc] Some refactoring of .td files X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=3b474d0d8844684c127cf0ced02fb6922da63212;p=llvm [AMDGPU][llvm-mc] Some refactoring of .td files Some custom Operands and AsmOperandClasses moved to proper place. No functional changes. Differential Revision: http://reviews.llvm.org/D20012 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268780 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td index 327868b9da0..523fdf8d5b1 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.td +++ b/lib/Target/AMDGPU/SIInstrInfo.td @@ -458,6 +458,33 @@ def sopp_brtarget : Operand { def const_ga : Operand; +def InterpSlot : Operand { + let PrintMethod = "printInterpSlot"; +} + +def SendMsgMatchClass : AsmOperandClass { + let Name = "SendMsg"; + let PredicateMethod = "isSendMsg"; + let ParserMethod = "parseSendMsgOp"; + let RenderMethod = "addImmOperands"; +} + +def SendMsgImm : Operand { + let PrintMethod = "printSendMsg"; + let ParserMatchClass = SendMsgMatchClass; +} + +def SWaitMatchClass : AsmOperandClass { + let Name = "SWaitCnt"; + let RenderMethod = "addImmOperands"; + let ParserMethod = "parseSWaitCntOps"; +} + +def WAIT_FLAG : Operand { + let ParserMatchClass = SWaitMatchClass; + let PrintMethod = "printWaitFlag"; +} + include "SIInstrFormats.td" include "VIInstrFormats.td" @@ -492,13 +519,6 @@ class NamedOperandU32 : Operand { let ParserMatchClass = MatchClass; } -def SendMsgMatchClass : AsmOperandClass { - let Name = "SendMsg"; - let PredicateMethod = "isSendMsg"; - let ParserMethod = "parseSendMsgOp"; - let RenderMethod = "addImmOperands"; -} - let OperandType = "OPERAND_IMMEDIATE" in { def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>; diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td index f369ab5f034..2c66e9aa6e7 100644 --- a/lib/Target/AMDGPU/SIInstructions.td +++ b/lib/Target/AMDGPU/SIInstructions.td @@ -18,15 +18,6 @@ int P20 = 1; } def INTERP : InterpSlots; -def InterpSlot : Operand { - let PrintMethod = "printInterpSlot"; -} - -def SendMsgImm : Operand { - let PrintMethod = "printSendMsg"; - let ParserMatchClass = SendMsgMatchClass; -} - def isGCN : Predicate<"Subtarget->getGeneration() " ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">, AssemblerPredicate<"FeatureGCN">; @@ -38,17 +29,6 @@ def isSI : Predicate<"Subtarget->getGeneration() " def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; -def SWaitMatchClass : AsmOperandClass { - let Name = "SWaitCnt"; - let RenderMethod = "addImmOperands"; - let ParserMethod = "parseSWaitCntOps"; -} - -def WAIT_FLAG : Operand { - let ParserMatchClass = SWaitMatchClass; - let PrintMethod = "printWaitFlag"; -} - let SubtargetPredicate = isGCN in { //===----------------------------------------------------------------------===//