From: Craig Topper <craig.topper@intel.com>
Date: Thu, 20 Jul 2017 19:29:58 +0000 (+0000)
Subject: [X86] Allow masks with more than 6 bits set on the x << (y & mask) optimization for... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=3acd890efb078836855afcd50fc832b291c0fdf1;p=llvm

[X86] Allow masks with more than 6 bits set on the x << (y & mask) optimization for the 64-bit memory shifts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308657 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index 9d188d3d5e5..3547c6526f1 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -1654,7 +1654,7 @@ multiclass MaskedShiftAmountPats<SDNode frag, string name> {
   // (shift x (and y, 63)) ==> (shift x, y)
   def : Pat<(frag GR64:$src1, (and CL, immShift64)),
             (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
-  def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
+  def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst),
             (!cast<Instruction>(name # "64mCL") addr:$dst)>;
 }
 
diff --git a/test/CodeGen/X86/shift-and.ll b/test/CodeGen/X86/shift-and.ll
index bb8eaa3c1cb..c61bff72ca6 100644
--- a/test/CodeGen/X86/shift-and.ll
+++ b/test/CodeGen/X86/shift-and.ll
@@ -99,7 +99,6 @@ define i64 @t5(i64 %t, i64 %val) nounwind {
 define void @t5ptr(i64 %t, i64* %ptr) nounwind {
 ; X64-LABEL: t5ptr:
 ; X64:       ## BB#0:
-; X64-NEXT:    andb $-65, %dil
 ; X64-NEXT:    movl %edi, %ecx
 ; X64-NEXT:    shrq %cl, (%rsi)
 ; X64-NEXT:    retq