From: Eugene Zelenko Date: Sat, 4 Feb 2017 00:36:49 +0000 (+0000) Subject: [Sparc] Fix some Include What You Use warnings; other minor fixes (NFC). X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=3a1cd31471952086ced3b946295bd4814019e558;p=llvm [Sparc] Fix some Include What You Use warnings; other minor fixes (NFC). This is preparation to reduce MCExpr.h dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294072 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index e775aa607b5..7e6dff6b789 100644 --- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -9,32 +9,49 @@ #include "MCTargetDesc/SparcMCExpr.h" #include "MCTargetDesc/SparcMCTargetDesc.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCParser/MCAsmLexer.h" +#include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCParser/MCTargetAsmParser.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/SMLoc.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Support/TargetRegistry.h" +#include +#include +#include +#include using namespace llvm; // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target // namespace. But SPARC backend uses "SP" as its namespace. namespace llvm { - namespace Sparc { +namespace Sparc { + using namespace SP; - } -} + +} // end namespace Sparc +} // end namespace llvm namespace { + class SparcOperand; -class SparcAsmParser : public MCTargetAsmParser { +class SparcAsmParser : public MCTargetAsmParser { MCAsmParser &Parser; /// @name Auto-generated Match Functions @@ -95,9 +112,10 @@ public: // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); } - }; +} // end anonymous namespace + static const MCPhysReg IntRegs[32] = { Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3, Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7, @@ -166,6 +184,8 @@ public: Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23, Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31}; +namespace { + /// SparcOperand - Instances of this class represent a parsed Sparc machine /// instruction. class SparcOperand : public MCParsedAsmOperand { @@ -219,6 +239,7 @@ private: struct ImmOp Imm; struct MemOp Mem; }; + public: SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} @@ -464,7 +485,7 @@ public: } }; -} // end namespace +} // end anonymous namespace bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions) { @@ -591,9 +612,8 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, llvm_unreachable("Implement any new match types added!"); } -bool SparcAsmParser:: -ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) -{ +bool SparcAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) { const AsmToken &Tok = Parser.getTok(); StartLoc = Tok.getLoc(); EndLoc = Tok.getEndLoc(); @@ -695,7 +715,7 @@ ParseDirective(AsmToken DirectiveID) bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) { if (getLexer().isNot(AsmToken::EndOfStatement)) { - for (;;) { + while (true) { const MCExpr *Value; if (getParser().parseExpression(Value)) return true; @@ -717,7 +737,6 @@ bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) { OperandMatchResultTy SparcAsmParser::parseMEMOperand(OperandVector &Operands) { - SMLoc S, E; unsigned BaseReg = 0; @@ -824,7 +843,6 @@ SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { OperandMatchResultTy SparcAsmParser::parseSparcAsmOperand(std::unique_ptr &Op, bool isCall) { - SMLoc S = Parser.getTok().getLoc(); SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); const MCExpr *EVal; @@ -910,11 +928,9 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr &Op, OperandMatchResultTy SparcAsmParser::parseBranchModifiers(OperandVector &Operands) { - // parse (,a|,pn|,pt)+ while (getLexer().is(AsmToken::Comma)) { - Parser.Lex(); // Eat the comma if (!getLexer().is(AsmToken::Identifier)) @@ -929,10 +945,8 @@ SparcAsmParser::parseBranchModifiers(OperandVector &Operands) { return MatchOperand_Success; } -bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, - unsigned &RegNo, - unsigned &RegKind) -{ +bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, unsigned &RegNo, + unsigned &RegKind) { int64_t intVal = 0; RegNo = 0; RegKind = SparcOperand::rk_None; @@ -1211,8 +1225,7 @@ static bool hasGOTReference(const MCExpr *Expr) { const SparcMCExpr * SparcAsmParser::adjustPICRelocation(SparcMCExpr::VariantKind VK, - const MCExpr *subExpr) -{ + const MCExpr *subExpr) { // When in PIC mode, "%lo(...)" and "%hi(...)" behave differently. // If the expression refers contains _GLOBAL_OFFSETE_TABLE, it is // actually a %pc10 or %pc22 relocation. Otherwise, they are interpreted @@ -1236,8 +1249,7 @@ SparcAsmParser::adjustPICRelocation(SparcMCExpr::VariantKind VK, } bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal, - SMLoc &EndLoc) -{ + SMLoc &EndLoc) { AsmToken Tok = Parser.getTok(); if (!Tok.is(AsmToken::Identifier)) return false; diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp index 86341c61d1e..684f66970db 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp @@ -11,20 +11,29 @@ // //===----------------------------------------------------------------------===// -#include "SparcMCExpr.h" #include "MCTargetDesc/SparcFixupKinds.h" +#include "SparcMCExpr.h" #include "SparcMCTargetDesc.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCFixup.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/SubtargetFeature.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/Endian.h" #include "llvm/Support/EndianStream.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include +#include using namespace llvm; @@ -33,17 +42,17 @@ using namespace llvm; STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); namespace { + class SparcMCCodeEmitter : public MCCodeEmitter { - SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete; - void operator=(const SparcMCCodeEmitter &) = delete; const MCInstrInfo &MCII; MCContext &Ctx; public: SparcMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) : MCII(mcii), Ctx(ctx) {} - - ~SparcMCCodeEmitter() override {} + SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete; + SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete; + ~SparcMCCodeEmitter() override = default; void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, @@ -79,13 +88,8 @@ private: void verifyInstructionPredicates(const MCInst &MI, uint64_t AvailableFeatures) const; }; -} // end anonymous namespace -MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII, - const MCRegisterInfo &MRI, - MCContext &Ctx) { - return new SparcMCCodeEmitter(MCII, Ctx); -} +} // end anonymous namespace void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, @@ -121,12 +125,10 @@ void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, ++MCNumEmitted; // Keep track of the # of mi's emitted. } - unsigned SparcMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { - if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); @@ -209,6 +211,7 @@ getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, (MCFixupKind)Sparc::fixup_sparc_br19)); return 0; } + unsigned SparcMCCodeEmitter:: getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, @@ -227,3 +230,9 @@ getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, #define ENABLE_INSTR_PREDICATE_VERIFIER #include "SparcGenMCCodeEmitter.inc" + +MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII, + const MCRegisterInfo &MRI, + MCContext &Ctx) { + return new SparcMCCodeEmitter(MCII, Ctx); +}