From: DRC Date: Wed, 13 Jul 2016 21:03:36 +0000 (-0500) Subject: AVX2: Perform additional checks for O/S support X-Git-Tag: 1.5.90~113 X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=3924ebceb52fc0fe61ac8981d66212d132510285;p=libjpeg-turbo AVX2: Perform additional checks for O/S support cpuid tells us whether the O/S uses extended state management via XSAVE/XRSTOR, but we have to call xgetbv to verify that it is using XSAVE/XRSTOR to manage the state of XMM/YMM registers. --- diff --git a/simd/jsimdcpu-64.asm b/simd/jsimdcpu-64.asm index d0c2e5b..78d7309 100644 --- a/simd/jsimdcpu-64.asm +++ b/simd/jsimdcpu-64.asm @@ -58,6 +58,12 @@ EXTN(jpeg_simd_cpu_support): test rcx, 1<<28 jz short .return ; CPU does not support AVX2 + xor rcx, rcx + xgetbv + test rax, 6 ; O/S does not manage XMM/YMM state + ; using XSAVE + jz short .return + or rdi, JSIMD_AVX2 .return: diff --git a/simd/jsimdcpu.asm b/simd/jsimdcpu.asm index 92782e2..827aefe 100644 --- a/simd/jsimdcpu.asm +++ b/simd/jsimdcpu.asm @@ -49,13 +49,13 @@ EXTN(jpeg_simd_cpu_support): pushfd pop eax xor eax, edx - jz short .return ; CPUID is not supported + jz near .return ; CPUID is not supported ; Check for MMX instruction support xor eax, eax cpuid test eax, eax - jz short .return + jz near .return xor eax, eax inc eax @@ -92,6 +92,12 @@ EXTN(jpeg_simd_cpu_support): test ecx, 1<<28 jz short .no_avx2 ; CPU does not support AVX2 + xor ecx, ecx + xgetbv + test eax, 6 ; O/S does not manage XMM/YMM state + ; using XSAVE + jz short .no_avx2 + or edi, JSIMD_AVX2 .no_avx2: