From: Chandler Carruth <chandlerc@gmail.com>
Date: Sat, 14 Jul 2018 00:52:09 +0000 (+0000)
Subject: [x86/SLH] Add an assert to catch if we ever end up trying to harden
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=383081c48d23bbc1bd2517f9e6699b716d675d0c;p=llvm

[x86/SLH] Add an assert to catch if we ever end up trying to harden
post-load a register that isn't valid for use with OR or SHRX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337078 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/lib/Target/X86/X86SpeculativeLoadHardening.cpp
index e5325cc542a..2bbb187b293 100644
--- a/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ b/lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -1533,6 +1533,14 @@ void X86SpeculativeLoadHardeningPass::hardenPostLoad(
   unsigned OrOpCodes[] = {X86::OR8rr, X86::OR16rr, X86::OR32rr, X86::OR64rr};
   unsigned OrOpCode = OrOpCodes[Log2_32(DefRegBytes)];
 
+#ifndef NDEBUG
+  const TargetRegisterClass *OrRegClasses[] = {
+      &X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32RegClass,
+      &X86::GR64RegClass};
+  assert(DefRC->hasSuperClassEq(OrRegClasses[Log2_32(DefRegBytes)]) &&
+         "Cannot define this register with OR instruction!");
+#endif
+
   unsigned SubRegImms[] = {X86::sub_8bit, X86::sub_16bit, X86::sub_32bit};
 
   auto GetStateRegInRC = [&](const TargetRegisterClass &RC) {