From: Simon Pilgrim Date: Tue, 5 Sep 2017 12:28:30 +0000 (+0000) Subject: [X86] Regenerate scalar rotation tests X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=34cbdf56ca38d83f31289108b95c7c737ea0e11a;p=llvm [X86] Regenerate scalar rotation tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312530 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/X86/rot32.ll b/test/CodeGen/X86/rot32.ll index 4f2ed2d61e8..305defeeea7 100644 --- a/test/CodeGen/X86/rot32.ll +++ b/test/CodeGen/X86/rot32.ll @@ -1,11 +1,16 @@ -; RUN: llc < %s -mtriple=i686-- -mcpu=corei7 | FileCheck %s -; RUN: llc < %s -mtriple=i686-- -mcpu=corei7-avx | FileCheck %s --check-prefix=SHLD -; RUN: llc < %s -mtriple=i686-- -mcpu=core-avx2 | FileCheck %s --check-prefix=BMI2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-- -mcpu=corei7 | FileCheck %s --check-prefix=ALL --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-- -mcpu=corei7-avx | FileCheck %s --check-prefix=ALL --check-prefix=SHLD +; RUN: llc < %s -mtriple=i686-- -mcpu=core-avx2 | FileCheck %s --check-prefix=ALL --check-prefix=BMI2 define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone { +; ALL-LABEL: foo: +; ALL: # BB#0: # %entry +; ALL-NEXT: movb {{[0-9]+}}(%esp), %cl +; ALL-NEXT: movl {{[0-9]+}}(%esp), %eax +; ALL-NEXT: roll %cl, %eax +; ALL-NEXT: retl entry: -; CHECK-LABEL: foo: -; CHECK: roll %cl %0 = shl i32 %x, %z %1 = sub i32 32, %z %2 = lshr i32 %x, %1 @@ -14,9 +19,14 @@ entry: } define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone { +; ALL-LABEL: bar: +; ALL: # BB#0: # %entry +; ALL-NEXT: movb {{[0-9]+}}(%esp), %cl +; ALL-NEXT: movl {{[0-9]+}}(%esp), %edx +; ALL-NEXT: movl {{[0-9]+}}(%esp), %eax +; ALL-NEXT: shldl %cl, %edx, %eax +; ALL-NEXT: retl entry: -; CHECK-LABEL: bar: -; CHECK: shldl %cl %0 = shl i32 %y, %z %1 = sub i32 32, %z %2 = lshr i32 %x, %1 @@ -25,9 +35,13 @@ entry: } define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone { +; ALL-LABEL: un: +; ALL: # BB#0: # %entry +; ALL-NEXT: movb {{[0-9]+}}(%esp), %cl +; ALL-NEXT: movl {{[0-9]+}}(%esp), %eax +; ALL-NEXT: rorl %cl, %eax +; ALL-NEXT: retl entry: -; CHECK-LABEL: un: -; CHECK: rorl %cl %0 = lshr i32 %x, %z %1 = sub i32 32, %z %2 = shl i32 %x, %1 @@ -36,9 +50,14 @@ entry: } define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone { +; ALL-LABEL: bu: +; ALL: # BB#0: # %entry +; ALL-NEXT: movb {{[0-9]+}}(%esp), %cl +; ALL-NEXT: movl {{[0-9]+}}(%esp), %edx +; ALL-NEXT: movl {{[0-9]+}}(%esp), %eax +; ALL-NEXT: shrdl %cl, %edx, %eax +; ALL-NEXT: retl entry: -; CHECK-LABEL: bu: -; CHECK: shrdl %cl %0 = lshr i32 %y, %z %1 = sub i32 32, %z %2 = shl i32 %x, %1 @@ -47,13 +66,23 @@ entry: } define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone { -entry: -; CHECK-LABEL: xfoo: -; CHECK: roll $7 +; X86-LABEL: xfoo: +; X86: # BB#0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: roll $7, %eax +; X86-NEXT: retl +; ; SHLD-LABEL: xfoo: -; SHLD: shldl $7 +; SHLD: # BB#0: # %entry +; SHLD-NEXT: movl {{[0-9]+}}(%esp), %eax +; SHLD-NEXT: shldl $7, %eax, %eax +; SHLD-NEXT: retl +; ; BMI2-LABEL: xfoo: -; BMI2: rorxl $25 +; BMI2: # BB#0: # %entry +; BMI2-NEXT: rorxl $25, {{[0-9]+}}(%esp), %eax +; BMI2-NEXT: retl +entry: %0 = lshr i32 %x, 25 %1 = shl i32 %x, 7 %2 = or i32 %0, %1 @@ -61,13 +90,26 @@ entry: } define i32 @xfoop(i32* %p) nounwind readnone { -entry: -; CHECK-LABEL: xfoop: -; CHECK: roll $7 +; X86-LABEL: xfoop: +; X86: # BB#0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl (%eax), %eax +; X86-NEXT: roll $7, %eax +; X86-NEXT: retl +; ; SHLD-LABEL: xfoop: -; SHLD: shldl $7 +; SHLD: # BB#0: # %entry +; SHLD-NEXT: movl {{[0-9]+}}(%esp), %eax +; SHLD-NEXT: movl (%eax), %eax +; SHLD-NEXT: shldl $7, %eax, %eax +; SHLD-NEXT: retl +; ; BMI2-LABEL: xfoop: -; BMI2: rorxl $25 +; BMI2: # BB#0: # %entry +; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax +; BMI2-NEXT: rorxl $25, (%eax), %eax +; BMI2-NEXT: retl +entry: %x = load i32, i32* %p %a = lshr i32 %x, 25 %b = shl i32 %x, 7 @@ -76,9 +118,13 @@ entry: } define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone { +; ALL-LABEL: xbar: +; ALL: # BB#0: # %entry +; ALL-NEXT: movl {{[0-9]+}}(%esp), %ecx +; ALL-NEXT: movl {{[0-9]+}}(%esp), %eax +; ALL-NEXT: shldl $7, %ecx, %eax +; ALL-NEXT: retl entry: -; CHECK-LABEL: xbar: -; CHECK: shldl $7 %0 = shl i32 %y, 7 %1 = lshr i32 %x, 25 %2 = or i32 %0, %1 @@ -86,13 +132,23 @@ entry: } define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone { -entry: -; CHECK-LABEL: xun: -; CHECK: roll $25 +; X86-LABEL: xun: +; X86: # BB#0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: roll $25, %eax +; X86-NEXT: retl +; ; SHLD-LABEL: xun: -; SHLD: shldl $25 +; SHLD: # BB#0: # %entry +; SHLD-NEXT: movl {{[0-9]+}}(%esp), %eax +; SHLD-NEXT: shldl $25, %eax, %eax +; SHLD-NEXT: retl +; ; BMI2-LABEL: xun: -; BMI2: rorxl $7 +; BMI2: # BB#0: # %entry +; BMI2-NEXT: rorxl $7, {{[0-9]+}}(%esp), %eax +; BMI2-NEXT: retl +entry: %0 = lshr i32 %x, 7 %1 = shl i32 %x, 25 %2 = or i32 %0, %1 @@ -100,13 +156,28 @@ entry: } define i32 @xunp(i32* %p) nounwind readnone { +; X86-LABEL: xunp: +; X86: # BB#0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl (%eax), %eax +; X86-NEXT: roll $25, %eax +; X86-NEXT: retl +; +; SHLD-LABEL: xunp: +; SHLD: # BB#0: # %entry +; SHLD-NEXT: movl {{[0-9]+}}(%esp), %eax +; SHLD-NEXT: movl (%eax), %eax +; SHLD-NEXT: shldl $25, %eax, %eax +; SHLD-NEXT: retl +; +; BMI2-LABEL: xunp: +; BMI2: # BB#0: # %entry +; BMI2-NEXT: movl {{[0-9]+}}(%esp), %eax +; BMI2-NEXT: rorxl $7, (%eax), %eax +; BMI2-NEXT: retl entry: -; CHECK-LABEL: xunp: -; CHECK: roll $25 ; shld-label: xunp: ; shld: shldl $25 -; BMI2-LABEL: xunp: -; BMI2: rorxl $7 %x = load i32, i32* %p %a = lshr i32 %x, 7 %b = shl i32 %x, 25 @@ -115,9 +186,13 @@ entry: } define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone { +; ALL-LABEL: xbu: +; ALL: # BB#0: # %entry +; ALL-NEXT: movl {{[0-9]+}}(%esp), %ecx +; ALL-NEXT: movl {{[0-9]+}}(%esp), %eax +; ALL-NEXT: shldl $25, %ecx, %eax +; ALL-NEXT: retl entry: -; CHECK-LABEL: xbu: -; CHECK: shldl $25 %0 = lshr i32 %y, 7 %1 = shl i32 %x, 25 %2 = or i32 %0, %1 diff --git a/test/CodeGen/X86/rot64.ll b/test/CodeGen/X86/rot64.ll index 382d242c4f0..b2e7d481d8c 100644 --- a/test/CodeGen/X86/rot64.ll +++ b/test/CodeGen/X86/rot64.ll @@ -1,11 +1,16 @@ -; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx | FileCheck %s --check-prefix=SHLD -; RUN: llc < %s -mtriple=x86_64-- -mcpu=core-avx2 | FileCheck %s --check-prefix=BMI2 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s --check-prefix=ALL --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx | FileCheck %s --check-prefix=ALL --check-prefix=SHLD +; RUN: llc < %s -mtriple=x86_64-- -mcpu=core-avx2 | FileCheck %s --check-prefix=ALL --check-prefix=BMI2 define i64 @foo(i64 %x, i64 %y, i64 %z) nounwind readnone { +; ALL-LABEL: foo: +; ALL: # BB#0: # %entry +; ALL-NEXT: movl %edx, %ecx +; ALL-NEXT: rolq %cl, %rdi +; ALL-NEXT: movq %rdi, %rax +; ALL-NEXT: retq entry: -; CHECK-LABEL: foo: -; CHECK: rolq %cl %0 = shl i64 %x, %z %1 = sub i64 64, %z %2 = lshr i64 %x, %1 @@ -14,9 +19,13 @@ entry: } define i64 @bar(i64 %x, i64 %y, i64 %z) nounwind readnone { +; ALL-LABEL: bar: +; ALL: # BB#0: # %entry +; ALL-NEXT: movl %edx, %ecx +; ALL-NEXT: shldq %cl, %rdi, %rsi +; ALL-NEXT: movq %rsi, %rax +; ALL-NEXT: retq entry: -; CHECK-LABEL: bar: -; CHECK: shldq %cl %0 = shl i64 %y, %z %1 = sub i64 64, %z %2 = lshr i64 %x, %1 @@ -25,9 +34,13 @@ entry: } define i64 @un(i64 %x, i64 %y, i64 %z) nounwind readnone { +; ALL-LABEL: un: +; ALL: # BB#0: # %entry +; ALL-NEXT: movl %edx, %ecx +; ALL-NEXT: rorq %cl, %rdi +; ALL-NEXT: movq %rdi, %rax +; ALL-NEXT: retq entry: -; CHECK-LABEL: un: -; CHECK: rorq %cl %0 = lshr i64 %x, %z %1 = sub i64 64, %z %2 = shl i64 %x, %1 @@ -36,9 +49,13 @@ entry: } define i64 @bu(i64 %x, i64 %y, i64 %z) nounwind readnone { +; ALL-LABEL: bu: +; ALL: # BB#0: # %entry +; ALL-NEXT: movl %edx, %ecx +; ALL-NEXT: shrdq %cl, %rdi, %rsi +; ALL-NEXT: movq %rsi, %rax +; ALL-NEXT: retq entry: -; CHECK-LABEL: bu: -; CHECK: shrdq %cl %0 = lshr i64 %y, %z %1 = sub i64 64, %z %2 = shl i64 %x, %1 @@ -47,13 +64,23 @@ entry: } define i64 @xfoo(i64 %x, i64 %y, i64 %z) nounwind readnone { -entry: -; CHECK-LABEL: xfoo: -; CHECK: rolq $7 +; X64-LABEL: xfoo: +; X64: # BB#0: # %entry +; X64-NEXT: rolq $7, %rdi +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: retq +; ; SHLD-LABEL: xfoo: -; SHLD: shldq $7 +; SHLD: # BB#0: # %entry +; SHLD-NEXT: shldq $7, %rdi, %rdi +; SHLD-NEXT: movq %rdi, %rax +; SHLD-NEXT: retq +; ; BMI2-LABEL: xfoo: -; BMI2: rorxq $57 +; BMI2: # BB#0: # %entry +; BMI2-NEXT: rorxq $57, %rdi, %rax +; BMI2-NEXT: retq +entry: %0 = lshr i64 %x, 57 %1 = shl i64 %x, 7 %2 = or i64 %0, %1 @@ -61,13 +88,23 @@ entry: } define i64 @xfoop(i64* %p) nounwind readnone { -entry: -; CHECK-LABEL: xfoop: -; CHECK: rolq $7 +; X64-LABEL: xfoop: +; X64: # BB#0: # %entry +; X64-NEXT: movq (%rdi), %rax +; X64-NEXT: rolq $7, %rax +; X64-NEXT: retq +; ; SHLD-LABEL: xfoop: -; SHLD: shldq $7 +; SHLD: # BB#0: # %entry +; SHLD-NEXT: movq (%rdi), %rax +; SHLD-NEXT: shldq $7, %rax, %rax +; SHLD-NEXT: retq +; ; BMI2-LABEL: xfoop: -; BMI2: rorxq $57 +; BMI2: # BB#0: # %entry +; BMI2-NEXT: rorxq $57, (%rdi), %rax +; BMI2-NEXT: retq +entry: %x = load i64, i64* %p %a = lshr i64 %x, 57 %b = shl i64 %x, 7 @@ -76,9 +113,12 @@ entry: } define i64 @xbar(i64 %x, i64 %y, i64 %z) nounwind readnone { +; ALL-LABEL: xbar: +; ALL: # BB#0: # %entry +; ALL-NEXT: shrdq $57, %rsi, %rdi +; ALL-NEXT: movq %rdi, %rax +; ALL-NEXT: retq entry: -; CHECK-LABEL: xbar: -; CHECK: shrdq $57 %0 = shl i64 %y, 7 %1 = lshr i64 %x, 57 %2 = or i64 %0, %1 @@ -86,13 +126,23 @@ entry: } define i64 @xun(i64 %x, i64 %y, i64 %z) nounwind readnone { -entry: -; CHECK-LABEL: xun: -; CHECK: rolq $57 +; X64-LABEL: xun: +; X64: # BB#0: # %entry +; X64-NEXT: rolq $57, %rdi +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: retq +; ; SHLD-LABEL: xun: -; SHLD: shldq $57 +; SHLD: # BB#0: # %entry +; SHLD-NEXT: shldq $57, %rdi, %rdi +; SHLD-NEXT: movq %rdi, %rax +; SHLD-NEXT: retq +; ; BMI2-LABEL: xun: -; BMI2: rorxq $7 +; BMI2: # BB#0: # %entry +; BMI2-NEXT: rorxq $7, %rdi, %rax +; BMI2-NEXT: retq +entry: %0 = lshr i64 %x, 7 %1 = shl i64 %x, 57 %2 = or i64 %0, %1 @@ -100,13 +150,23 @@ entry: } define i64 @xunp(i64* %p) nounwind readnone { -entry: -; CHECK-LABEL: xunp: -; CHECK: rolq $57 +; X64-LABEL: xunp: +; X64: # BB#0: # %entry +; X64-NEXT: movq (%rdi), %rax +; X64-NEXT: rolq $57, %rax +; X64-NEXT: retq +; ; SHLD-LABEL: xunp: -; SHLD: shldq $57 +; SHLD: # BB#0: # %entry +; SHLD-NEXT: movq (%rdi), %rax +; SHLD-NEXT: shldq $57, %rax, %rax +; SHLD-NEXT: retq +; ; BMI2-LABEL: xunp: -; BMI2: rorxq $7 +; BMI2: # BB#0: # %entry +; BMI2-NEXT: rorxq $7, (%rdi), %rax +; BMI2-NEXT: retq +entry: %x = load i64, i64* %p %a = lshr i64 %x, 7 %b = shl i64 %x, 57 @@ -115,9 +175,12 @@ entry: } define i64 @xbu(i64 %x, i64 %y, i64 %z) nounwind readnone { +; ALL-LABEL: xbu: +; ALL: # BB#0: # %entry +; ALL-NEXT: shldq $57, %rsi, %rdi +; ALL-NEXT: movq %rdi, %rax +; ALL-NEXT: retq entry: -; CHECK-LABEL: xbu: -; CHECK: shldq $57 %0 = lshr i64 %y, 7 %1 = shl i64 %x, 57 %2 = or i64 %0, %1