From: Tim Renouf <tpr.llvm@botech.co.uk>
Date: Mon, 24 Jun 2019 17:35:20 +0000 (+0000)
Subject: [AMDGPU] Allow any value in unused src0 field in v_nop
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=33a237946ed5d58681209966457c876de818c28c;p=llvm

[AMDGPU] Allow any value in unused src0 field in v_nop

Summary:
The LLVM disassembler assumes that the unused src0 operand of v_nop is
zero. Other tools can put another value in that field, which is still
valid. This commit fixes the LLVM disassembler to recognize such an
encoding as v_nop, in the same way as we already do for s_getpc.

Differential Revision: https://reviews.llvm.org/D63724

Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364208 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/VOP1Instructions.td b/lib/Target/AMDGPU/VOP1Instructions.td
index a916091d6fb..6bc416ed7d4 100644
--- a/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/lib/Target/AMDGPU/VOP1Instructions.td
@@ -14,7 +14,7 @@ class VOP1e <bits<8> op, VOPProfile P> : Enc32 {
   bits<8> vdst;
   bits<9> src0;
 
-  let Inst{8-0}   = !if(P.HasSrc0, src0{8-0}, 0);
+  let Inst{8-0}   = !if(P.HasSrc0, src0{8-0}, ?);
   let Inst{16-9}  = op;
   let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
   let Inst{31-25} = 0x3f; //encoding
diff --git a/test/MC/Disassembler/AMDGPU/nop.txt b/test/MC/Disassembler/AMDGPU/nop.txt
index 0305765e6f5..d27c0bc6a58 100644
--- a/test/MC/Disassembler/AMDGPU/nop.txt
+++ b/test/MC/Disassembler/AMDGPU/nop.txt
@@ -2,3 +2,6 @@
 
 # CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
 0x00 0x00 0x00 0x7e
+
+# CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
+0x80 0x00 0x00 0x7e
diff --git a/test/MC/Disassembler/AMDGPU/vop1.txt b/test/MC/Disassembler/AMDGPU/vop1.txt
index 02540848796..3e65f6142b7 100644
--- a/test/MC/Disassembler/AMDGPU/vop1.txt
+++ b/test/MC/Disassembler/AMDGPU/vop1.txt
@@ -3,6 +3,9 @@
 # CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
 0x00 0x00 0x00 0x7e
 
+# CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
+0x80 0x00 0x00 0x7e
+
 # CHECK: v_clrexcp                       ; encoding: [0x00,0x6a,0x00,0x7e]
 0x00 0x6a 0x00 0x7e
 
diff --git a/test/MC/Disassembler/AMDGPU/vop1_vi.txt b/test/MC/Disassembler/AMDGPU/vop1_vi.txt
index c42c0a62810..8e1a13e2589 100644
--- a/test/MC/Disassembler/AMDGPU/vop1_vi.txt
+++ b/test/MC/Disassembler/AMDGPU/vop1_vi.txt
@@ -6,6 +6,9 @@
 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
 0x00 0x00 0x00 0x7e
 
+# VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+0x80 0x00 0x00 0x7e
+
 # VI:   v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
 0x00 0x6a 0x00 0x7e