From: Craig Topper <craig.topper@intel.com>
Date: Fri, 16 Aug 2019 04:47:44 +0000 (+0000)
Subject: [X86] Manually reimplement getTargetInsertSubreg in X86DAGToDAGISel::matchBitExtract... 
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=338d0f7a28c1075442a7b4f51a68b620c85c4720;p=llvm

[X86] Manually reimplement getTargetInsertSubreg in X86DAGToDAGISel::matchBitExtract so we can call insertDAGNode on the target constant.

This is needed to maintain the topological sort order.

Fixes PR42992.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369084 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 364f54ca5aa..46886419421 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -3333,8 +3333,12 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
   SDValue ImplDef = SDValue(
       CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i32), 0);
   insertDAGNode(*CurDAG, SDValue(Node, 0), ImplDef);
-  NBits = CurDAG->getTargetInsertSubreg(X86::sub_8bit, DL, MVT::i32, ImplDef,
-                                        NBits);
+
+  SDValue SRIdxVal = CurDAG->getTargetConstant(X86::sub_8bit, DL, MVT::i32);
+  insertDAGNode(*CurDAG, SDValue(Node, 0), SRIdxVal);
+  NBits = SDValue(
+      CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::i32, ImplDef,
+                             NBits, SRIdxVal), 0);
   insertDAGNode(*CurDAG, SDValue(Node, 0), NBits);
 
   if (Subtarget->hasBMI2()) {
diff --git a/test/CodeGen/X86/pr42992.ll b/test/CodeGen/X86/pr42992.ll
new file mode 100644
index 00000000000..f85b5921b10
--- /dev/null
+++ b/test/CodeGen/X86/pr42992.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=bmi2 | FileCheck %s
+
+define i32 @hoge(i32 %a) {
+; CHECK-LABEL: hoge:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    movl $15, %eax
+; CHECK-NEXT:    bzhil %edi, %eax, %eax
+; CHECK-NEXT:    shll $8, %eax
+; CHECK-NEXT:    retq
+bb:
+  %tmp3 = shl nsw i32 -1, %a
+  %tmp4 = xor i32 %tmp3, -1
+  %tmp5 = shl i32 %tmp4, 8
+  %tmp6 = and i32 %tmp5, 3840
+  ret i32 %tmp6
+}