From: Peter Johnson <peter@tortall.net>
Date: Sat, 2 Feb 2008 19:23:17 +0000 (-0000)
Subject: Revert r2029.  According to both AMD64 and Intel 64 instruction set
X-Git-Tag: v0.7.0~26
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=2fe53b2c299bf8292b7780105742ac357bcf8224;p=yasm

Revert r2029.  According to both AMD64 and Intel 64 instruction set
references, REX + 90h opcode is not NOP, but a valid XCHG:

"The x86 architecture commonly uses the XCHG EAX, EAX instruction (opcode
90h) as a one-byte NOP. In 64-bit mode, the processor treats opcode 90h as
a true NOP only if it would exchange rAX with itself. Without this special
handling, the instruction would zero-extend the upper 32 bits of RAX, and
thus it would not be a true nooperation.  Opcode 90h can still be used to
exchange rAX and r8 if the appropriate REX prefix is used."

Noticed by: nasm64developer@users.sf.net

svn path=/trunk/yasm/; revision=2031
---

diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index bb1ec5fe..fd923d4f 100755
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -1357,12 +1357,12 @@ add_group("xchg",
     opersize=16,
     opcode=[0x90],
     operands=[Operand(type="Areg", size=16, dest=None),
-              Operand(type="RegNotR8", size=16, dest="Op0Add")])
+              Operand(type="Reg", size=16, dest="Op0Add")])
 add_group("xchg",
     suffix="w",
     opersize=16,
     opcode=[0x90],
-    operands=[Operand(type="RegNotR8", size=16, dest="Op0Add"),
+    operands=[Operand(type="Reg", size=16, dest="Op0Add"),
               Operand(type="Areg", size=16, dest=None)])
 add_group("xchg",
     suffix="w",
@@ -1396,12 +1396,12 @@ add_group("xchg",
     opersize=32,
     opcode=[0x90],
     operands=[Operand(type="Areg", size=32, dest=None),
-              Operand(type="RegNotR8", size=32, dest="Op0Add")])
+              Operand(type="Reg", size=32, dest="Op0Add")])
 add_group("xchg",
     suffix="l",
     opersize=32,
     opcode=[0x90],
-    operands=[Operand(type="RegNotR8", size=32, dest="Op0Add"),
+    operands=[Operand(type="Reg", size=32, dest="Op0Add"),
               Operand(type="Areg", size=32, dest=None)])
 add_group("xchg",
     suffix="l",
@@ -1428,12 +1428,12 @@ add_group("xchg",
     opersize=64,
     opcode=[0x90],
     operands=[Operand(type="Areg", size=64, dest=None),
-              Operand(type="RegNotR8", size=64, dest="Op0Add")])
+              Operand(type="Reg", size=64, dest="Op0Add")])
 add_group("xchg",
     suffix="q",
     opersize=64,
     opcode=[0x90],
-    operands=[Operand(type="RegNotR8", size=64, dest="Op0Add"),
+    operands=[Operand(type="Reg", size=64, dest="Op0Add"),
               Operand(type="Areg", size=64, dest=None)])
 add_group("xchg",
     suffix="q",
diff --git a/modules/arch/x86/tests/xchg64.hex b/modules/arch/x86/tests/xchg64.hex
index d052b668..44adfca8 100644
--- a/modules/arch/x86/tests/xchg64.hex
+++ b/modules/arch/x86/tests/xchg64.hex
@@ -24,13 +24,11 @@ c0
 66 
 90 
 66 
-44 
-87 
-c0 
+41 
+90 
 66 
 41 
-87 
-c0 
+90 
 66 
 41 
 91 
@@ -39,23 +37,19 @@ c0
 91 
 87 
 c0 
-44 
-87 
-c0 
 41 
-87 
-c0 
+90 
+41 
+90 
 41 
 91 
 41 
 91 
 90 
-4c 
-87 
-c0 
 49 
-87 
-c0 
+90 
+49 
+90 
 49 
 91 
 49 
diff --git a/modules/arch/x86/x86id.c b/modules/arch/x86/x86id.c
index 874ad010..d17f045c 100644
--- a/modules/arch/x86/x86id.c
+++ b/modules/arch/x86/x86id.c
@@ -105,9 +105,7 @@ enum x86_operand_type {
     /* EAX memory operand only (EA) [special case for SVM skinit opcode] */
     OPT_MemEAX = 26,
     /* SIMDReg with value equal to operand 0 SIMDReg */
-    OPT_SIMDRegMatch0 = 27,
-    /* Reg with value != 8 [special case for xchg r8, rax] */
-    OPT_RegNotR8 = 28
+    OPT_SIMDRegMatch0 = 27
 };
 
 enum x86_operand_size {
@@ -808,25 +806,6 @@ x86_find_match(x86_id_insn *id_insn, yasm_insn_operand **ops,
                         mismatch = 1;
                     break;
                 }
-                case OPT_RegNotR8:
-                    if (op->type != YASM_INSN__OPERAND_REG ||
-                        ((op->data.reg&0xFUL) == 8))
-                        mismatch = 1;
-                    else {
-                        switch ((x86_expritem_reg_size)(op->data.reg&~0xFUL)) {
-                            case X86_REG8:
-                            case X86_REG8X:
-                            case X86_REG16:
-                            case X86_REG32:
-                            case X86_REG64:
-                            case X86_FPUREG:
-                                break;
-                            default:
-                                mismatch = 1;
-                                break;
-                        }
-                    }
-                    break;
                 default:
                     yasm_internal_error(N_("invalid operand type"));
             }