From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Thu, 20 Jun 2019 21:33:57 +0000 (+0000)
Subject: AMDGPU: Add DS GWS sema builtins
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=2f4434368bf2bfdae1b4fd7c88ac4a9f845e41ce;p=clang

AMDGPU: Add DS GWS sema builtins

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@363986 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/clang/Basic/BuiltinsAMDGPU.def b/include/clang/Basic/BuiltinsAMDGPU.def
index a8aadff770..49002f0f79 100644
--- a/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/include/clang/Basic/BuiltinsAMDGPU.def
@@ -47,6 +47,9 @@ BUILTIN(__builtin_amdgcn_s_dcache_inv, "v", "n")
 BUILTIN(__builtin_amdgcn_buffer_wbinvl1, "v", "n")
 BUILTIN(__builtin_amdgcn_ds_gws_init, "vUiUi", "n")
 BUILTIN(__builtin_amdgcn_ds_gws_barrier, "vUiUi", "n")
+BUILTIN(__builtin_amdgcn_ds_gws_sema_v, "vUi", "n")
+BUILTIN(__builtin_amdgcn_ds_gws_sema_br, "vUiUi", "n")
+BUILTIN(__builtin_amdgcn_ds_gws_sema_p, "vUi", "n")
 
 // FIXME: Need to disallow constant address space.
 BUILTIN(__builtin_amdgcn_div_scale, "dddbb*", "n")
@@ -108,6 +111,7 @@ BUILTIN(__builtin_amdgcn_ds_consume, "ii*3", "n")
 //===----------------------------------------------------------------------===//
 TARGET_BUILTIN(__builtin_amdgcn_s_dcache_inv_vol, "v", "n", "ci-insts")
 TARGET_BUILTIN(__builtin_amdgcn_buffer_wbinvl1_vol, "v", "n", "ci-insts")
+TARGET_BUILTIN(__builtin_amdgcn_ds_gws_sema_release_all, "vUi", "n", "ci-insts")
 
 //===----------------------------------------------------------------------===//
 // Interpolation builtins.
diff --git a/test/CodeGenOpenCL/builtins-amdgcn-ci.cl b/test/CodeGenOpenCL/builtins-amdgcn-ci.cl
index 41275268db..3045225e10 100644
--- a/test/CodeGenOpenCL/builtins-amdgcn-ci.cl
+++ b/test/CodeGenOpenCL/builtins-amdgcn-ci.cl
@@ -3,6 +3,8 @@
 // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu fiji -S -emit-llvm -o - %s | FileCheck %s
 // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx906 -S -emit-llvm -o - %s | FileCheck %s
 
+typedef unsigned int uint;
+
 // CHECK-LABEL: @test_s_dcache_inv_vol
 // CHECK: call void @llvm.amdgcn.s.dcache.inv.vol(
 void test_s_dcache_inv_vol()
@@ -17,3 +19,9 @@ void test_buffer_wbinvl1_vol()
   __builtin_amdgcn_buffer_wbinvl1_vol();
 }
 
+// CHECK-LABEL: @test_gws_sema_release_all(
+// CHECK: call void @llvm.amdgcn.ds.gws.sema.release.all(i32 %id)
+void test_gws_sema_release_all(uint id)
+{
+  __builtin_amdgcn_ds_gws_sema_release_all(id);
+}
diff --git a/test/CodeGenOpenCL/builtins-amdgcn.cl b/test/CodeGenOpenCL/builtins-amdgcn.cl
index 27a91a18cc..3b710a81b1 100644
--- a/test/CodeGenOpenCL/builtins-amdgcn.cl
+++ b/test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -560,6 +560,24 @@ kernel void test_gws_barrier(uint value, uint id) {
   __builtin_amdgcn_ds_gws_barrier(value, id);
 }
 
+// CHECK-LABEL: @test_gws_sema_v(
+// CHECK: call void @llvm.amdgcn.ds.gws.sema.v(i32 %id)
+kernel void test_gws_sema_v(uint id) {
+  __builtin_amdgcn_ds_gws_sema_v(id);
+}
+
+// CHECK-LABEL: @test_gws_sema_br(
+// CHECK: call void @llvm.amdgcn.ds.gws.sema.br(i32 %value, i32 %id)
+kernel void test_gws_sema_br(uint value, uint id) {
+  __builtin_amdgcn_ds_gws_sema_br(value, id);
+}
+
+// CHECK-LABEL: @test_gws_sema_p(
+// CHECK: call void @llvm.amdgcn.ds.gws.sema.p(i32 %id)
+kernel void test_gws_sema_p(uint id) {
+  __builtin_amdgcn_ds_gws_sema_p(id);
+}
+
 // CHECK-DAG: [[$WI_RANGE]] = !{i32 0, i32 1024}
 // CHECK-DAG: attributes #[[$NOUNWIND_READONLY:[0-9]+]] = { nounwind readonly }
 // CHECK-DAG: attributes #[[$READ_EXEC_ATTRS]] = { convergent }
diff --git a/test/SemaOpenCL/builtins-amdgcn-error-ci.cl b/test/SemaOpenCL/builtins-amdgcn-error-ci.cl
index 2f656582be..d8ebeeacab 100644
--- a/test/SemaOpenCL/builtins-amdgcn-error-ci.cl
+++ b/test/SemaOpenCL/builtins-amdgcn-error-ci.cl
@@ -1,8 +1,9 @@
 // REQUIRES: amdgpu-registered-target
 // RUN: %clang_cc1 -triple amdgcn-- -target-cpu tahiti -verify -S -o - %s
 
-void test_ci_biltins()
+void test_ci_builtins()
 {
   __builtin_amdgcn_s_dcache_inv_vol(); // expected-error {{'__builtin_amdgcn_s_dcache_inv_vol' needs target feature ci-insts}}
   __builtin_amdgcn_buffer_wbinvl1_vol(); // expected-error {{'__builtin_amdgcn_buffer_wbinvl1_vol' needs target feature ci-insts}}
+  __builtin_amdgcn_ds_gws_sema_release_all(0); // expected-error {{'__builtin_amdgcn_ds_gws_sema_release_all' needs target feature ci-insts}}
 }