From: Sanjay Patel Date: Fri, 11 Aug 2017 22:05:33 +0000 (+0000) Subject: [x86] regenerate test checks, add 64-bit run; NFC X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=2e808dea5155053283417c9aa3290a0f3c4168eb;p=llvm [x86] regenerate test checks, add 64-bit run; NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310767 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/X86/rot16.ll b/test/CodeGen/X86/rot16.ll index de08a3e35be..809e3f714e5 100644 --- a/test/CodeGen/X86/rot16.ll +++ b/test/CodeGen/X86/rot16.ll @@ -1,85 +1,163 @@ -; RUN: llc < %s -mtriple=i686-- -mcpu=generic | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 -define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone { -entry: -; CHECK-LABEL: foo: -; CHECK: rolw %cl - %0 = shl i16 %x, %z - %1 = sub i16 16, %z - %2 = lshr i16 %x, %1 - %3 = or i16 %2, %0 - ret i16 %3 +define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind { +; X32-LABEL: foo: +; X32: # BB#0: +; X32-NEXT: movb {{[0-9]+}}(%esp), %cl +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X32-NEXT: rolw %cl, %ax +; X32-NEXT: retl +; +; X64-LABEL: foo: +; X64: # BB#0: +; X64-NEXT: movl %edx, %ecx +; X64-NEXT: shldw %cl, %di, %di +; X64-NEXT: movl %edi, %eax +; X64-NEXT: retq + %t0 = shl i16 %x, %z + %t1 = sub i16 16, %z + %t2 = lshr i16 %x, %t1 + %t3 = or i16 %t2, %t0 + ret i16 %t3 } -define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone { -entry: -; CHECK-LABEL: bar: -; CHECK: shldw %cl - %0 = shl i16 %y, %z - %1 = sub i16 16, %z - %2 = lshr i16 %x, %1 - %3 = or i16 %2, %0 - ret i16 %3 +define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind { +; X32-LABEL: bar: +; X32: # BB#0: +; X32-NEXT: movb {{[0-9]+}}(%esp), %cl +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %edx +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X32-NEXT: shldw %cl, %dx, %ax +; X32-NEXT: retl +; +; X64-LABEL: bar: +; X64: # BB#0: +; X64-NEXT: movl %edx, %ecx +; X64-NEXT: shldw %cl, %di, %si +; X64-NEXT: movl %esi, %eax +; X64-NEXT: retq + %t0 = shl i16 %y, %z + %t1 = sub i16 16, %z + %t2 = lshr i16 %x, %t1 + %t3 = or i16 %t2, %t0 + ret i16 %t3 } -define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone { -entry: -; CHECK-LABEL: un: -; CHECK: rorw %cl - %0 = lshr i16 %x, %z - %1 = sub i16 16, %z - %2 = shl i16 %x, %1 - %3 = or i16 %2, %0 - ret i16 %3 +define i16 @un(i16 %x, i16 %y, i16 %z) nounwind { +; X32-LABEL: un: +; X32: # BB#0: +; X32-NEXT: movb {{[0-9]+}}(%esp), %cl +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X32-NEXT: rorw %cl, %ax +; X32-NEXT: retl +; +; X64-LABEL: un: +; X64: # BB#0: +; X64-NEXT: movl %edx, %ecx +; X64-NEXT: shrdw %cl, %di, %di +; X64-NEXT: movl %edi, %eax +; X64-NEXT: retq + %t0 = lshr i16 %x, %z + %t1 = sub i16 16, %z + %t2 = shl i16 %x, %t1 + %t3 = or i16 %t2, %t0 + ret i16 %t3 } -define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone { -entry: -; CHECK-LABEL: bu: -; CHECK: shrdw - %0 = lshr i16 %y, %z - %1 = sub i16 16, %z - %2 = shl i16 %x, %1 - %3 = or i16 %2, %0 - ret i16 %3 +define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind { +; X32-LABEL: bu: +; X32: # BB#0: +; X32-NEXT: movb {{[0-9]+}}(%esp), %cl +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %edx +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X32-NEXT: shrdw %cl, %dx, %ax +; X32-NEXT: retl +; +; X64-LABEL: bu: +; X64: # BB#0: +; X64-NEXT: movl %edx, %ecx +; X64-NEXT: shrdw %cl, %di, %si +; X64-NEXT: movl %esi, %eax +; X64-NEXT: retq + %t0 = lshr i16 %y, %z + %t1 = sub i16 16, %z + %t2 = shl i16 %x, %t1 + %t3 = or i16 %t2, %t0 + ret i16 %t3 } -define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone { -entry: -; CHECK-LABEL: xfoo: -; CHECK: rolw $5 - %0 = lshr i16 %x, 11 - %1 = shl i16 %x, 5 - %2 = or i16 %0, %1 - ret i16 %2 +define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind { +; X32-LABEL: xfoo: +; X32: # BB#0: +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X32-NEXT: rolw $5, %ax +; X32-NEXT: retl +; +; X64-LABEL: xfoo: +; X64: # BB#0: +; X64-NEXT: rolw $5, %di +; X64-NEXT: movl %edi, %eax +; X64-NEXT: retq + %t0 = lshr i16 %x, 11 + %t1 = shl i16 %x, 5 + %t2 = or i16 %t0, %t1 + ret i16 %t2 } -define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone { -entry: -; CHECK-LABEL: xbar: -; CHECK: shldw $5 - %0 = shl i16 %y, 5 - %1 = lshr i16 %x, 11 - %2 = or i16 %0, %1 - ret i16 %2 +define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind { +; X32-LABEL: xbar: +; X32: # BB#0: +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X32-NEXT: shldw $5, %cx, %ax +; X32-NEXT: retl +; +; X64-LABEL: xbar: +; X64: # BB#0: +; X64-NEXT: shldw $5, %di, %si +; X64-NEXT: movl %esi, %eax +; X64-NEXT: retq + %t0 = shl i16 %y, 5 + %t1 = lshr i16 %x, 11 + %t2 = or i16 %t0, %t1 + ret i16 %t2 } -define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone { -entry: -; CHECK-LABEL: xun: -; CHECK: rolw $11 - %0 = lshr i16 %x, 5 - %1 = shl i16 %x, 11 - %2 = or i16 %0, %1 - ret i16 %2 +define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind { +; X32-LABEL: xun: +; X32: # BB#0: +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X32-NEXT: rolw $11, %ax +; X32-NEXT: retl +; +; X64-LABEL: xun: +; X64: # BB#0: +; X64-NEXT: rolw $11, %di +; X64-NEXT: movl %edi, %eax +; X64-NEXT: retq + %t0 = lshr i16 %x, 5 + %t1 = shl i16 %x, 11 + %t2 = or i16 %t0, %t1 + ret i16 %t2 } -define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone { -entry: -; CHECK-LABEL: xbu: -; CHECK: shldw $11 - %0 = lshr i16 %y, 5 - %1 = shl i16 %x, 11 - %2 = or i16 %0, %1 - ret i16 %2 +define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind { +; X32-LABEL: xbu: +; X32: # BB#0: +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx +; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax +; X32-NEXT: shldw $11, %cx, %ax +; X32-NEXT: retl +; +; X64-LABEL: xbu: +; X64: # BB#0: +; X64-NEXT: shldw $11, %si, %di +; X64-NEXT: movl %edi, %eax +; X64-NEXT: retq + %t0 = lshr i16 %y, 5 + %t1 = shl i16 %x, 11 + %t2 = or i16 %t0, %t1 + ret i16 %t2 }