From: David Majnemer <david.majnemer@gmail.com>
Date: Thu, 16 Jul 2015 03:13:02 +0000 (+0000)
Subject: [Intrin.h] Use compiler builtins to model memory barriers
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=2e7e2fb00424f9dd27642b7fdc1f2d1fc2bc3328;p=clang

[Intrin.h] Use compiler builtins to model memory barriers

_ReadBarrier, _WriteBarrier, and _ReadWriteBarrier are essentially
memory barriers of one form or another.  Model these as
atomic_signal_fence(ATOMIC_SEQ_CST).

__faststorefence is a curious intrinsic.  It's single purpose seems to
an alternative to mfence when that instruction is slow.  However, mfence
is not always slow and is, in general, preferable to a 'lock or'
sequence on certain CPUs.  Give the compiler freedom to select the best
sequence to get a fence.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@242378 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Headers/Intrin.h b/lib/Headers/Intrin.h
index 24b3eae8bf..67c8a63265 100644
--- a/lib/Headers/Intrin.h
+++ b/lib/Headers/Intrin.h
@@ -770,27 +770,25 @@ _InterlockedCompareExchange64(__int64 volatile *_Destination,
 /*----------------------------------------------------------------------------*\
 |* Barriers
 \*----------------------------------------------------------------------------*/
-#if defined(__i386__) || defined(__x86_64__)
 static __inline__ void __DEFAULT_FN_ATTRS
 __attribute__((__deprecated__("use other intrinsics or C++11 atomics instead")))
 _ReadWriteBarrier(void) {
-  __asm__ volatile ("" : : : "memory");
+  __atomic_signal_fence(__ATOMIC_SEQ_CST);
 }
 static __inline__ void __DEFAULT_FN_ATTRS
 __attribute__((__deprecated__("use other intrinsics or C++11 atomics instead")))
 _ReadBarrier(void) {
-  __asm__ volatile ("" : : : "memory");
+  __atomic_signal_fence(__ATOMIC_SEQ_CST);
 }
 static __inline__ void __DEFAULT_FN_ATTRS
 __attribute__((__deprecated__("use other intrinsics or C++11 atomics instead")))
 _WriteBarrier(void) {
-  __asm__ volatile ("" : : : "memory");
+  __atomic_signal_fence(__ATOMIC_SEQ_CST);
 }
-#endif
 #ifdef __x86_64__
 static __inline__ void __DEFAULT_FN_ATTRS
 __faststorefence(void) {
-  __asm__ volatile("lock orq $0, (%%rsp)" : : : "memory");
+  __atomic_thread_fence(__ATOMIC_SEQ_CST);
 }
 #endif
 /*----------------------------------------------------------------------------*\