From: Chad Rosier <mcrosier@codeaurora.org>
Date: Mon, 11 Nov 2013 19:11:19 +0000 (+0000)
Subject: [AArch64] The shift right/left and insert immediate builtins expect 3
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=2bd8af5888d8cad4b56185f2d38659eb3cb1272b;p=clang

[AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@194407 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td
index 32bca46726..cfde22717f 100644
--- a/include/clang/Basic/arm_neon.td
+++ b/include/clang/Basic/arm_neon.td
@@ -859,9 +859,9 @@ def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">;
 def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">;
 
 // Shift Right And Insert (Immediate)
-def SCALAR_SRI_N: SInst<"vsri_n", "ssi", "SlSUl">;
+def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">;
 // Shift Left And Insert (Immediate)
-def SCALAR_SLI_N: SInst<"vsli_n", "ssi", "SlSUl">;
+def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">;
 
 // Signed/Unsigned Saturating Shift Right Narrow (Immediate)
 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">;
diff --git a/test/CodeGen/aarch64-neon-intrinsics.c b/test/CodeGen/aarch64-neon-intrinsics.c
index c59b6ec94f..3030bd96a2 100644
--- a/test/CodeGen/aarch64-neon-intrinsics.c
+++ b/test/CodeGen/aarch64-neon-intrinsics.c
@@ -7616,28 +7616,28 @@ int64_t test_vqshlud_n_s64(int64_t a) {
   return (int64_t)vqshlud_n_s64(a, 63);
 }
 
-int64_t test_vsrid_n_s64(int64_t a) {
+int64_t test_vsrid_n_s64(int64_t a, int64_t b) {
 // CHECK-LABEL: test_vsrid_n_s64
 // CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63
-  return (int64_t)vsrid_n_s64(a, 63);
+  return (int64_t)vsrid_n_s64(a, b, 63);
 }
 
-uint64_t test_vsrid_n_u64(uint64_t a) {
+uint64_t test_vsrid_n_u64(uint64_t a, uint64_t b) {
 // CHECK-LABEL: test_vsrid_n_u64
 // CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63
-  return (uint64_t)vsrid_n_u64(a, 63);
+  return (uint64_t)vsrid_n_u64(a, b, 63);
 }
 
-int64_t test_vslid_n_s64(int64_t a) {
+int64_t test_vslid_n_s64(int64_t a, int64_t b) {
 // CHECK-LABEL: test_vslid_n_s64
 // CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63
-  return (int64_t)vslid_n_s64(a, 63);
+  return (int64_t)vslid_n_s64(a, b, 63);
 }
 
-uint64_t test_vslid_n_u64(uint64_t a) {
+uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
 // CHECK-LABEL: test_vslid_n_u64
 // CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63
-  return (uint64_t)vslid_n_u64(a, 63);
+  return (uint64_t)vslid_n_u64(a, b, 63);
 }
 
 int8_t test_vqshrnh_n_s16(int16_t a) {