From: Sanjay Patel <spatel@rotateright.com>
Date: Sat, 23 Mar 2019 15:00:52 +0000 (+0000)
Subject: [x86] reduce code duplication; NFC
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=2b7218d3777f6b01e44cbeef9a20a656e9fa11e6;p=llvm

[x86] reduce code duplication; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356836 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index beaf9b4e0d1..fe7f1a9e6a7 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -23926,17 +23926,19 @@ static SDValue lowerAddSub(SDValue Op, SelectionDAG &DAG,
 
 static SDValue LowerADDSAT_SUBSAT(SDValue Op, SelectionDAG &DAG) {
   MVT VT = Op.getSimpleValueType();
+  SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
   if (VT.getScalarType() == MVT::i1) {
     SDLoc dl(Op);
     switch (Op.getOpcode()) {
     default: llvm_unreachable("Expected saturated arithmetic opcode");
     case ISD::UADDSAT:
     case ISD::SADDSAT:
-      return DAG.getNode(ISD::OR, dl, VT, Op.getOperand(0), Op.getOperand(1));
+      // *addsat i1 X, Y --> X | Y
+      return DAG.getNode(ISD::OR, dl, VT, X, Y);
     case ISD::USUBSAT:
     case ISD::SSUBSAT:
-      return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0),
-                         DAG.getNOT(dl, Op.getOperand(1), VT));
+      // *subsat i1 X, Y --> X & ~Y
+      return DAG.getNode(ISD::AND, dl, VT, X, DAG.getNOT(dl, Y, VT));
     }
   }