From: Ron Lieberman <ronl@codeaurora.org>
Date: Mon, 2 Oct 2017 00:16:15 +0000 (+0000)
Subject: [Hexagon] Patch to Extract i1 element from vector of i1
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=29fbd6fadb6d2747686e041597a8c0fd30057640;p=llvm

[Hexagon] Patch to Extract i1 element from vector of i1

This patch extracts 1 element from vector consisting
of elements of size 1 bit at given index.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314641 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp
index fcde4224a00..0d2b27f089e 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2750,7 +2750,13 @@ HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
     MVT SVT = VecVT.getSimpleVT();
     uint64_t W = CW->getZExtValue();
 
-    if (W == 32) {
+    if (W == 1) {
+      MVT LocVT = MVT::getIntegerVT(SVT.getSizeInBits());
+      SDValue VecCast = DAG.getNode(ISD::BITCAST, dl, LocVT, Vec);
+      SDValue Shifted = DAG.getNode(ISD::SRA, dl, LocVT, VecCast, Offset);
+      return DAG.getNode(ISD::AND, dl, LocVT, Shifted,
+                         DAG.getConstant(1, dl, LocVT));
+    } else if (W == 32) {
       // Translate this node into EXTRACT_SUBREG.
       unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
 
diff --git a/test/CodeGen/Hexagon/vect/vect-extract-i1.ll b/test/CodeGen/Hexagon/vect/vect-extract-i1.ll
new file mode 100644
index 00000000000..8bcf1768b88
--- /dev/null
+++ b/test/CodeGen/Hexagon/vect/vect-extract-i1.ll
@@ -0,0 +1,9 @@
+; RUN: llc -march=hexagon < %s
+
+define i1 @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
+entry:
+	%0 = add <4 x i8> %a, %b
+        %1 = bitcast <4 x i8> %0 to <32 x i1>
+        %2 = extractelement <32 x i1> %1, i32 0
+	ret i1 %2
+}