From: Philip Reames Date: Sat, 1 Jun 2019 03:09:28 +0000 (+0000) Subject: [LoopPred] Eliminate a redundant/confusing cover function [NFC] X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=26777bcd975afd53878ae78a0782e54a2c91837c;p=llvm [LoopPred] Eliminate a redundant/confusing cover function [NFC] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362284 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Transforms/Scalar/LoopPredication.cpp b/lib/Transforms/Scalar/LoopPredication.cpp index 1503b5000c1..dfecacfcb78 100644 --- a/lib/Transforms/Scalar/LoopPredication.cpp +++ b/lib/Transforms/Scalar/LoopPredication.cpp @@ -257,13 +257,7 @@ class LoopPredication { LoopICmp LatchCheck; bool isSupportedStep(const SCEV* Step); - Optional parseLoopICmp(ICmpInst *ICI) { - return parseLoopICmp(ICI->getPredicate(), ICI->getOperand(0), - ICI->getOperand(1)); - } - Optional parseLoopICmp(ICmpInst::Predicate Pred, Value *LHS, - Value *RHS); - + Optional parseLoopICmp(ICmpInst *ICI); Optional parseLoopLatchICmp(); /// Return an insertion point suitable for inserting a safe to speculate @@ -383,8 +377,11 @@ PreservedAnalyses LoopPredicationPass::run(Loop &L, LoopAnalysisManager &AM, } Optional -LoopPredication::parseLoopICmp(ICmpInst::Predicate Pred, Value *LHS, - Value *RHS) { +LoopPredication::parseLoopICmp(ICmpInst *ICI) { + auto Pred = ICI->getPredicate(); + auto *LHS = ICI->getOperand(0); + auto *RHS = ICI->getOperand(1); + const SCEV *LHSS = SE->getSCEV(LHS); if (isa(LHSS)) return None; @@ -818,27 +815,30 @@ Optional LoopPredication::parseLoopLatchICmp() { return None; } - ICmpInst::Predicate Pred; - Value *LHS, *RHS; - BasicBlock *TrueDest, *FalseDest; - - if (!match(LoopLatch->getTerminator(), - m_Br(m_ICmp(Pred, m_Value(LHS), m_Value(RHS)), TrueDest, - FalseDest))) { + auto *BI = dyn_cast(LoopLatch->getTerminator()); + if (!BI) { LLVM_DEBUG(dbgs() << "Failed to match the latch terminator!\n"); return None; } + BasicBlock *TrueDest = BI->getSuccessor(0); + BasicBlock *FalseDest = BI->getSuccessor(1); assert((TrueDest == L->getHeader() || FalseDest == L->getHeader()) && "One of the latch's destinations must be the header"); - if (TrueDest != L->getHeader()) - Pred = ICmpInst::getInversePredicate(Pred); - auto Result = parseLoopICmp(Pred, LHS, RHS); + auto *ICI = dyn_cast(BI->getCondition()); + if (!ICI || !BI->isConditional()) { + LLVM_DEBUG(dbgs() << "Failed to match the latch condition!\n"); + return None; + } + auto Result = parseLoopICmp(ICI); if (!Result) { LLVM_DEBUG(dbgs() << "Failed to parse the loop latch condition!\n"); return None; } + if (TrueDest != L->getHeader()) + Result->Pred = ICmpInst::getInversePredicate(Result->Pred); + // Check affine first, so if it's not we don't try to compute the step // recurrence. if (!Result->IV->isAffine()) { @@ -869,6 +869,7 @@ Optional LoopPredication::parseLoopLatchICmp() { << ")!\n"); return None; } + return Result; }