From: Craig Topper Date: Wed, 22 Mar 2017 04:03:53 +0000 (+0000) Subject: [InstCombine] Teach SimplifyDemandedUseBits to shrink Constants on the left side... X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=2612791ba8f92ac0726623bc7df3eef6f59be922;p=llvm [InstCombine] Teach SimplifyDemandedUseBits to shrink Constants on the left side of subtracts Summary: Subtracts can have constants on the left side, but we don't shrink them based on demanded bits. This patch fixes that to match the right hand side. Reviewers: davide, majnemer, spatel, sanjoy, hfinkel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31119 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298478 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index b4cc534dd53..41d4a4820bf 100644 --- a/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -533,7 +533,8 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, // Right fill the mask of bits for this ADD/SUB to demand the most // significant bit and all those below it. APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ)); - if (SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps, + if (ShrinkDemandedConstant(I, 0, DemandedFromOps) || + SimplifyDemandedBits(I->getOperandUse(0), DemandedFromOps, LHSKnownZero, LHSKnownOne, Depth + 1) || ShrinkDemandedConstant(I, 1, DemandedFromOps) || SimplifyDemandedBits(I->getOperandUse(1), DemandedFromOps, diff --git a/test/Transforms/InstCombine/sub.ll b/test/Transforms/InstCombine/sub.ll index b756f6a571e..03946c7dbe6 100644 --- a/test/Transforms/InstCombine/sub.ll +++ b/test/Transforms/InstCombine/sub.ll @@ -701,3 +701,46 @@ define i8 @bool_sext_sub_nuw(i8 %x, i1 %y) { ret i8 %sub } +define i32 @test49(i32 %X) { +; CHECK-LABEL: @test49( +; CHECK-NEXT: [[SUB:%.*]] = sub i32 1, [[X:%.*]] +; CHECK-NEXT: [[RES:%.*]] = and i32 [[SUB]], 64 +; CHECK-NEXT: ret i32 [[RES]] +; + %sub = sub i32 129, %X + %res = and i32 %sub, 64 + ret i32 %res +} + +define i32 @test50(i32 %X) { +; CHECK-LABEL: @test50( +; CHECK-NEXT: [[SUB:%.*]] = sub i32 1, [[X:%.*]] +; CHECK-NEXT: [[RES:%.*]] = and i32 [[SUB]], 127 +; CHECK-NEXT: ret i32 [[RES]] +; + %sub = sub i32 129, %X + %res = and i32 %sub, 127 + ret i32 %res +} + +define i32 @test51(i32 %X) { +; CHECK-LABEL: @test51( +; CHECK-NEXT: [[SUB:%.*]] = sub i32 126, [[X:%.*]] +; CHECK-NEXT: [[RES:%.*]] = and i32 [[SUB]], 64 +; CHECK-NEXT: ret i32 [[RES]] +; + %sub = sub i32 254, %X + %res = and i32 %sub, 64 + ret i32 %res +} + +define i32 @test52(i32 %X) { +; CHECK-LABEL: @test52( +; CHECK-NEXT: [[SUB:%.*]] = sub i32 126, [[X:%.*]] +; CHECK-NEXT: [[RES:%.*]] = and i32 [[SUB]], 127 +; CHECK-NEXT: ret i32 [[RES]] +; + %sub = sub i32 254, %X + %res = and i32 %sub, 127 + ret i32 %res +}