From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Thu, 6 Oct 2016 10:13:23 +0000 (+0000)
Subject: AMDGPU: Partially fix reported code size for some instructions
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=25ec2590590076f846f902ea0b5daac812b37e53;p=llvm

AMDGPU: Partially fix reported code size for some instructions

These ones need to have the size on the pseudo instruction set for
getInstSizeInBytes to work correctly. These also have a statically
known size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283437 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index e9bc1191cba..ef7321402da 100644
--- a/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -346,7 +346,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
       if (MI.isDebugValue())
         continue;
 
-      CodeSize += TII->getInstSizeInBytes(MI);
+      if (isVerbose())
+        CodeSize += TII->getInstSizeInBytes(MI);
 
       unsigned numOperands = MI.getNumOperands();
       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
diff --git a/lib/Target/AMDGPU/BUFInstructions.td b/lib/Target/AMDGPU/BUFInstructions.td
index 220dd8deeb6..01be18baba6 100644
--- a/lib/Target/AMDGPU/BUFInstructions.td
+++ b/lib/Target/AMDGPU/BUFInstructions.td
@@ -66,6 +66,7 @@ class MTBUF_Pseudo <string opName, dag outs, dag ins,
 
   let isPseudo = 1;
   let isCodeGenOnly = 1;
+  let Size = 8;
   let UseNamedOperandTable = 1;
 
   string Mnemonic = opName;
@@ -77,7 +78,6 @@ class MTBUF_Pseudo <string opName, dag outs, dag ins,
   let Uses = [EXEC];
 
   let hasSideEffects = 0;
-  let UseNamedOperandTable = 1;
   let SchedRW = [WriteVMEM];
 }
 
@@ -159,6 +159,7 @@ class MUBUF_Pseudo <string opName, dag outs, dag ins,
 
   let isPseudo = 1;
   let isCodeGenOnly = 1;
+  let Size = 8;
   let UseNamedOperandTable = 1;
 
   string Mnemonic = opName;
diff --git a/lib/Target/AMDGPU/DSInstructions.td b/lib/Target/AMDGPU/DSInstructions.td
index 06103f3056d..8adb7f6bb34 100644
--- a/lib/Target/AMDGPU/DSInstructions.td
+++ b/lib/Target/AMDGPU/DSInstructions.td
@@ -15,6 +15,7 @@ class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
 
   let LGKM_CNT = 1;
   let DS = 1;
+  let Size = 8;
   let UseNamedOperandTable = 1;
   let Uses = [M0, EXEC];
 
diff --git a/lib/Target/AMDGPU/SOPInstructions.td b/lib/Target/AMDGPU/SOPInstructions.td
index 5a42016074b..d31002b999a 100644
--- a/lib/Target/AMDGPU/SOPInstructions.td
+++ b/lib/Target/AMDGPU/SOPInstructions.td
@@ -575,8 +575,8 @@ def S_SETREG_B32 : SOPK_Pseudo <
 def S_SETREG_IMM32_B32 : SOPK_Pseudo <
   "s_setreg_imm32_b32",
   (outs), (ins i32imm:$imm, hwreg:$simm16),
-  "$simm16, $imm"
-> {
+  "$simm16, $imm"> {
+  let Size = 8; // Unlike every other SOPK instruction.
   let has_sdst = 0;
 }
 
@@ -688,6 +688,7 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
   let hasSideEffects = 0;
   let SALU = 1;
   let SOPP = 1;
+  let Size = 4;
   let SchedRW = [WriteSALU];
 
   let UseNamedOperandTable = 1;