From: Simon Tatham <simon.tatham@arm.com>
Date: Tue, 25 Jun 2019 16:49:32 +0000 (+0000)
Subject: [ARM] Support inline assembler constraints for MVE.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=23849425dc9b0a8d030a84242699d8addbeaad6d;p=clang

[ARM] Support inline assembler constraints for MVE.

"To" selects an odd-numbered GPR, and "Te" an even one. There are some
8.1-M instructions that have one too few bits in their register fields
and require registers of particular parity, without necessarily using
a consecutive even/odd pair.

Also, the constraint letter "t" should select an MVE q-register, when
MVE is present. This didn't need any source changes, but some extra
tests have been added.

Reviewers: dmgreen, samparker, SjoerdMeijer

Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D60709

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@364331 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Basic/Targets/ARM.cpp b/lib/Basic/Targets/ARM.cpp
index 7ed2158a47..ceab4e7f95 100644
--- a/lib/Basic/Targets/ARM.cpp
+++ b/lib/Basic/Targets/ARM.cpp
@@ -900,6 +900,16 @@ bool ARMTargetInfo::validateAsmConstraint(
   case 'Q': // A memory address that is a single base register.
     Info.setAllowsMemory();
     return true;
+  case 'T':
+    switch (Name[1]) {
+    default:
+      break;
+    case 'e': // Even general-purpose register
+    case 'o': // Odd general-purpose register
+      Info.setAllowsRegister();
+      Name++;
+      return true;
+    }
   case 'U': // a memory reference...
     switch (Name[1]) {
     case 'q': // ...ARMV4 ldrsb
@@ -923,6 +933,7 @@ std::string ARMTargetInfo::convertConstraint(const char *&Constraint) const {
   std::string R;
   switch (*Constraint) {
   case 'U': // Two-character constraint; add "^" hint for later parsing.
+  case 'T':
     R = std::string("^") + std::string(Constraint, 2);
     Constraint++;
     break;
diff --git a/test/CodeGen/arm-asm.c b/test/CodeGen/arm-asm.c
index bd2fe11993..d2ae1ed762 100644
--- a/test/CodeGen/arm-asm.c
+++ b/test/CodeGen/arm-asm.c
@@ -6,3 +6,21 @@ int t1() {
     __asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv" (k) : "s15");
     return 0;
 }
+
+// CHECK-LABEL: @even_reg_constraint_Te
+int even_reg_constraint_Te(void) {
+  int acc = 0;
+  // CHECK: vaddv{{.*\^Te}}
+  asm("vaddv.s8 %0, Q0"
+      : "+Te" (acc));
+  return acc;
+}
+
+// CHECK-LABEL: @odd_reg_constraint_To
+int odd_reg_constraint_To(void) {
+  int eacc = 0, oacc = 0;
+  // CHECK: vaddlv{{.*\^To}}
+  asm("vaddlv.s8 %0, %1, Q0"
+      : "+Te" (eacc), "+To" (oacc));
+  return oacc;
+}