From: Sander de Smalen Date: Sat, 28 Jul 2018 14:18:11 +0000 (+0000) Subject: [AArch64][SVE] Asm: Support for PFALSE and PTEST instructions. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=234c23e0a025de2ee741242b19da521e7bfff715;p=llvm [AArch64][SVE] Asm: Support for PFALSE and PTEST instructions. This patch adds PFALSE (unconditionally sets all elements of the predicate to false) and PTEST (set the status flags for the predicate). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338198 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index c3d916b2bbf..e0013529a26 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -239,6 +239,9 @@ let Predicates = [HasSVE] in { defm BRKB_PPmP : sve_int_break_m<0b101, "brkb">; defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs">; + def PTEST_PP : sve_int_ptest<0b010000, "ptest">; + def PFALSE : sve_int_pfalse<0b000000, "pfalse">; + def AND_PPzPP : sve_int_pred_log<0b0000, "and">; def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">; def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">; diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index 85396f5bfdb..b00af930dc1 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -281,6 +281,47 @@ let Predicates = [HasSVE] in { } +//===----------------------------------------------------------------------===// +// SVE Predicate Misc Group +//===----------------------------------------------------------------------===// + +class sve_int_pfalse opc, string asm> +: I<(outs PPR8:$Pd), (ins), + asm, "\t$Pd", + "", + []>, Sched<[]> { + bits<4> Pd; + let Inst{31-24} = 0b00100101; + let Inst{23-22} = opc{5-4}; + let Inst{21-19} = 0b011; + let Inst{18-16} = opc{3-1}; + let Inst{15-10} = 0b111001; + let Inst{9} = opc{0}; + let Inst{8-4} = 0b00000; + let Inst{3-0} = Pd; +} + +class sve_int_ptest opc, string asm> +: I<(outs), (ins PPRAny:$Pg, PPR8:$Pn), + asm, "\t$Pg, $Pn", + "", + []>, Sched<[]> { + bits<4> Pg; + bits<4> Pn; + let Inst{31-24} = 0b00100101; + let Inst{23-22} = opc{5-4}; + let Inst{21-19} = 0b010; + let Inst{18-16} = opc{3-1}; + let Inst{15-14} = 0b11; + let Inst{13-10} = Pg; + let Inst{9} = opc{0}; + let Inst{8-5} = Pn; + let Inst{4-0} = 0b00000; + + let Defs = [NZCV]; +} + + //===----------------------------------------------------------------------===// // SVE Predicate Count Group //===----------------------------------------------------------------------===// @@ -4202,3 +4243,4 @@ multiclass sve_int_break_m opc, string asm> { multiclass sve_int_break_z opc, string asm> { def NAME : sve_int_break; } + diff --git a/test/MC/AArch64/SVE/pfalse-diagnostics.s b/test/MC/AArch64/SVE/pfalse-diagnostics.s new file mode 100644 index 00000000000..1a4047d8d80 --- /dev/null +++ b/test/MC/AArch64/SVE/pfalse-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +pfalse p15.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: pfalse p15.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/pfalse.s b/test/MC/AArch64/SVE/pfalse.s new file mode 100644 index 00000000000..b1385d8b863 --- /dev/null +++ b/test/MC/AArch64/SVE/pfalse.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +pfalse p15.b +// CHECK-INST: pfalse p15.b +// CHECK-ENCODING: [0x0f,0xe4,0x18,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 0f e4 18 25 diff --git a/test/MC/AArch64/SVE/ptest-diagnostics.s b/test/MC/AArch64/SVE/ptest-diagnostics.s new file mode 100644 index 00000000000..f03bf4c60f8 --- /dev/null +++ b/test/MC/AArch64/SVE/ptest-diagnostics.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Only .b is supported + +ptest p15, p15.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: ptest p15, p15.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/test/MC/AArch64/SVE/ptest.s b/test/MC/AArch64/SVE/ptest.s new file mode 100644 index 00000000000..29622c08c92 --- /dev/null +++ b/test/MC/AArch64/SVE/ptest.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ptest p15, p0.b +// CHECK-INST: ptest p15, p0.b +// CHECK-ENCODING: [0x00,0xfc,0x50,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 fc 50 25 + +ptest p15, p15.b +// CHECK-INST: ptest p15, p15.b +// CHECK-ENCODING: [0xe0,0xfd,0x50,0x25] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 fd 50 25