From: Matheus Almeida Date: Mon, 21 Oct 2013 11:47:56 +0000 (+0000) Subject: [mips][msa] Fix definition of SLD instruction. X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=22dd997f6dbdef0841f22f52b38cad79ea16c07a;p=clang [mips][msa] Fix definition of SLD instruction. The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/clang/Basic/BuiltinsMips.def b/include/clang/Basic/BuiltinsMips.def index cf198f6939..7711c1d6fd 100644 --- a/include/clang/Basic/BuiltinsMips.def +++ b/include/clang/Basic/BuiltinsMips.def @@ -774,10 +774,10 @@ BUILTIN(__builtin_msa_shf_b, "V16cV16cIUi", "nc") BUILTIN(__builtin_msa_shf_h, "V8sV8sIUi", "nc") BUILTIN(__builtin_msa_shf_w, "V4iV4iIUi", "nc") -BUILTIN(__builtin_msa_sld_b, "V16cV16cV16c", "nc") -BUILTIN(__builtin_msa_sld_h, "V8sV8sV8s", "nc") -BUILTIN(__builtin_msa_sld_w, "V4iV4iV4i", "nc") -BUILTIN(__builtin_msa_sld_d, "V2LLiV2LLiV2LLi", "nc") +BUILTIN(__builtin_msa_sld_b, "V16cV16cUi", "nc") +BUILTIN(__builtin_msa_sld_h, "V8sV8sUi", "nc") +BUILTIN(__builtin_msa_sld_w, "V4iV4iUi", "nc") +BUILTIN(__builtin_msa_sld_d, "V2LLiV2LLiUi", "nc") BUILTIN(__builtin_msa_sldi_b, "V16cV16cIUi", "nc") BUILTIN(__builtin_msa_sldi_h, "V8sV8sIUi", "nc") diff --git a/test/CodeGen/builtins-mips-msa.c b/test/CodeGen/builtins-mips-msa.c index 2ff161aa98..51508ee8ac 100644 --- a/test/CodeGen/builtins-mips-msa.c +++ b/test/CodeGen/builtins-mips-msa.c @@ -688,10 +688,10 @@ void test(void) { v8i16_r = __builtin_msa_shf_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.shf.h( v4i32_r = __builtin_msa_shf_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.shf.w( - v16i8_r = __builtin_msa_sld_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.sld.b( - v8i16_r = __builtin_msa_sld_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.sld.h( - v4i32_r = __builtin_msa_sld_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.sld.w( - v2i64_r = __builtin_msa_sld_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.sld.d( + v16i8_r = __builtin_msa_sld_b(v16i8_a, 10); // CHECK: call <16 x i8> @llvm.mips.sld.b( + v8i16_r = __builtin_msa_sld_h(v8i16_a, 10); // CHECK: call <8 x i16> @llvm.mips.sld.h( + v4i32_r = __builtin_msa_sld_w(v4i32_a, 10); // CHECK: call <4 x i32> @llvm.mips.sld.w( + v2i64_r = __builtin_msa_sld_d(v2i64_a, 10); // CHECK: call <2 x i64> @llvm.mips.sld.d( v16i8_r = __builtin_msa_sldi_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.sldi.b( v8i16_r = __builtin_msa_sldi_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.sldi.h(