From: Ivan Grokhotkov <ivan@espressif.com>
Date: Sat, 29 Sep 2018 02:54:06 +0000 (+0800)
Subject: bootloader: don’t reload RTC_FAST DRAM after deep sleep
X-Git-Tag: v3.2-beta1~84^2~3
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=22b840f3df1f23d1f17f12bca2dafd676d7aaf28;p=esp-idf

bootloader: don’t reload RTC_FAST DRAM after deep sleep

When CONFIG_ESP32_RTCDATA_IN_FAST_MEM is enabled, RTC data is placed
into RTC_FAST memory region, viewed from the data bus. However the
bootloader was missing a check that this region should not be
overwritten after deep sleep, which caused .rtc.bss segment to loose
its contents after wakeup.
---

diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c
index 3cce328654..98d5a341b2 100644
--- a/components/bootloader_support/src/esp_image_format.c
+++ b/components/bootloader_support/src/esp_image_format.c
@@ -468,11 +468,15 @@ static bool should_load(uint32_t load_addr)
 
     if (!load_rtc_memory) {
         if (load_addr >= SOC_RTC_IRAM_LOW && load_addr < SOC_RTC_IRAM_HIGH) {
-            ESP_LOGD(TAG, "Skipping RTC code segment at 0x%08x\n", load_addr);
+            ESP_LOGD(TAG, "Skipping RTC fast memory segment at 0x%08x\n", load_addr);
+            return false;
+        }
+        if (load_addr >= SOC_RTC_DRAM_LOW && load_addr < SOC_RTC_DRAM_HIGH) {
+            ESP_LOGD(TAG, "Skipping RTC fast memory segment at 0x%08x\n", load_addr);
             return false;
         }
         if (load_addr >= SOC_RTC_DATA_LOW && load_addr < SOC_RTC_DATA_HIGH) {
-            ESP_LOGD(TAG, "Skipping RTC data segment at 0x%08x\n", load_addr);
+            ESP_LOGD(TAG, "Skipping RTC slow memory segment at 0x%08x\n", load_addr);
             return false;
         }
     }
diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h
index 59d171f3bc..ff90df5420 100644
--- a/components/soc/esp32/include/soc/soc.h
+++ b/components/soc/esp32/include/soc/soc.h
@@ -288,6 +288,8 @@
 #define SOC_IRAM_HIGH   0x400A0000
 #define SOC_RTC_IRAM_LOW  0x400C0000
 #define SOC_RTC_IRAM_HIGH 0x400C2000
+#define SOC_RTC_DRAM_LOW  0x3FF80000
+#define SOC_RTC_DRAM_HIGH 0x3FF82000
 #define SOC_RTC_DATA_LOW  0x50000000
 #define SOC_RTC_DATA_HIGH 0x50002000