From: Tim Northover <tnorthover@apple.com>
Date: Mon, 2 Nov 2015 19:32:23 +0000 (+0000)
Subject: Fix va_arg on watchOS.
X-Git-Url: https://granicus.if.org/sourcecode?a=commitdiff_plain;h=1ee399bcf1a8c6e6e1fed1d645cdcadb04208a61;p=clang

Fix va_arg on watchOS.

As in other contexts, alignments can go up to 16 bytes in a va_list.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@251821 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
index 9b5ac4fc6c..0131f9dbb1 100644
--- a/lib/CodeGen/TargetInfo.cpp
+++ b/lib/CodeGen/TargetInfo.cpp
@@ -5301,6 +5301,10 @@ Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
              getABIKind() == ARMABIInfo::AAPCS) {
     TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
     TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
+  } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
+    // ARMv7k allows type alignment up to 16 bytes.
+    TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
+    TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
   } else {
     TyAlignForABI = CharUnits::fromQuantity(4);
   }
diff --git a/test/CodeGen/armv7k-abi.c b/test/CodeGen/armv7k-abi.c
index 93c0f0ca25..9b57de8727 100644
--- a/test/CodeGen/armv7k-abi.c
+++ b/test/CodeGen/armv7k-abi.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv7k-apple-watchos2.0 -target-abi aapcs16 %s -o - -emit-llvm | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv7k-apple-watchos2.0 -target-abi aapcs16 -target-cpu cortex-a7 %s -o - -emit-llvm | FileCheck %s
+
+#include <arm_neon.h>
 
 // Make sure 64 and 128 bit types are naturally aligned by the v7k ABI:
 
@@ -80,9 +82,12 @@ typedef struct {
 // CHECK: define [2 x i32] @return_oddly_sized_struct()
 OddlySizedStruct return_oddly_sized_struct() {}
 
-// CHECK: define double @test_va_arg(i8* %l)
-// CHECK:   load double, double*
-double test_va_arg(__builtin_va_list l) {
-  return __builtin_va_arg(l, double);
+// CHECK: define <4 x float> @test_va_arg_vec(i8* %l)
+// CHECK:   [[ALIGN_TMP:%.*]] = add i32 {{%.*}}, 15
+// CHECK:   [[ALIGNED:%.*]] = and i32 [[ALIGN_TMP]], -16
+// CHECK:   [[ALIGNED_I8:%.*]] = inttoptr i32 [[ALIGNED]] to i8*
+// CHECK:   [[ALIGNED_VEC:%.*]] = bitcast i8* [[ALIGNED_I8]] to <4 x float>
+// CHECK:   load <4 x float>, <4 x float>* [[ALIGNED_VEC]], align 16
+float32x4_t test_va_arg_vec(__builtin_va_list l) {
+  return __builtin_va_arg(l, float32x4_t);
 }
-